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April 2017 • The PCB Magazine 67 tern plate micro-etch to ensure optimum plat- ing adhesion. Developing Another possible source of copper-to-copper peelers has its genesis in the resist developing process. These are: • Over-developing • Under-developing • Poor rinsing after developing • Excessive hold time between resist lamination and develop With respect to overdeveloping, check the temperature of developing as well as the pH level in the developer solution. Higher pH and temperatures can lead to overdeveloping. This in turn leads to the potential for the exposed resist to leach from the side walls and onto the surfaces to be plated. In addition, one can man- age the breakpoint of developing to occur fur- ther along in the chamber. Under-developing will result in resist resi- dues and adhesion promoters remaining on the copper surface. Again, adjust the breakpoint to insure sufficient removal of the unexposed re- sist. Adjust developer pH and operating temper- ature per suppliers' recommendations. At the end of the day, chemical processing of printed circuit boards requires good rinsing with a high quantity of high-quality water. The alkaline nature of resist developing solutions requires warm water rinses as alkaline residues do not rinse very well. A good rule to follow to achieve adequate rinsing is the rinse chamber length should be at least 50% of the developer chamber length. Counterflow rinsing with two, if not three, rinse chambers using incoming tap water is also recommended. Counterflow rinsing will help reduce the pH of the first water rinse. Typically, the first rinse will have the highest pH due to dragout from the developer chamber. Finally, do not underestimate the hold time between lamination and developing. Excessive hold times (usually 12−14 hours or more) will lead to resist lock-in. This results in difficult to remove resist further increasing the tendency to cause copper-to-copper adhesion failures. If this is the case, a more aggressive acidic cleaner is required. Summary Follow good shop practices in terms of sur- face preparation, electroless copper plating thickness and resist developing parameters. Op- timal surface preparation utilizing cleaners and micro-etches is critical to eliminating copper- to-copper peeling. In addition, over- and under- developing create their own set of process con- straints. Pay very close attention to developer pH, operating temperature and break point. Finally, rinsing after develop with warm tap water is necessary to remove alkaline residues lurking on the resist sidewalls and traces. PCB Michael Carano is VP of technol- ogy and business development for RBP Chemical Technology. To reach Carano, or read past columns, click here. COPPER-TO-COPPER PEELING Understanding the electrical performance of flexible circuits at high- end digital transmission frequencies presents a growing challenge. The HDPUG High-Frequency Flex project is studying the effect of different design features, specifically cross hatched ground planes, on signal in- tegrity for flexible printed circuit boards operating at frequencies up to 20 GHz. Jonathan Weldon, RF Applications Engineer at DuPont Elec- tronic Materials, discusses some of the results of the program. Click here to view the interview. RTW IPC APEX EXPO: Impact of Cross-Hatched Ground Planes on HF Electrical Performance of Flex Circuits

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