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April 2017 • The PCB Magazine 39 PCB TECHNOLOGY REQUIREMENTS FOR MILLIMETER-WAVE INTERCONNECT AND ANTENNA curacy in the order ± 20 µm) there is the need to gather accurate X/Y measurement data and compensate dimension change in the CAM data. Measurement and compensation must be repeated at outer-layer formation. The corollary is the dimensional change must be measured and compensated over the course of multilayer board (MLB) manufacture. Experience showed that, despite refining the CAM data, LCP-based MLB exhibit discrete dimensional stability variation. Back-end machining, say, for cavity formation, must make use of localized optical targets (fiducials) to satisfy positional accuracy requirements. Laser-based metrology and laser direct imaging (LDI) are mandatory capabilities. Circuit Requirements Consider that each aspect of the circuitry must be defined in relation to minimizing sig- nal degradation (loss). Transmission line toler- ance is a key factor. In MiWaveS typically ±10% was specified. For features <150 µm, this means ±15 µm which challenges PCB manufacturing capabilities for multilayer RF boards. Millime- ter wave circuits on a PCB use very narrow line widths around 100 µm or even 75 µm. A single microstrip or coplanar line impedance itself does not change very rapidly due to geometry variations but problems can arise with flip-chip component pads, filter circuits and antenna center frequency change due to under- or over- etching. The line mismatches are also cascaded that can exacerbate problems due to standing waves between circuit blocks. Repeatability of the etching tolerance is also important for opti- mization of mmW circuits. An attribute of low-loss materials is the use of low-profile copper-foil; this helps the etch process, which is isotropic in nature. Naturally the aspects of a subtractive process versus semi- additive (or fully-additive) have a major bearing on feature resolution capability. Regardless, the processor must have the opportunity to deploy liquid photoresist (i.e., <10 µm thickness) and the right level of etching control. As mentioned in the Technology Overview section earlier, feature-to-feature accuracy is an important factor for managing transmission losses. It is not uncommon in mmW type work to have blind or buried vias placed within 20 µm location alignment to an underlying feature (pad for example). This is complicated in achiev- ing the requirement over an 18" x 12" (457 mm x 305 mm) manufacturing panel and on ma- terials with inconsistent dimensional stability. In such a requirement, innerlayers are bonded sequentially. Optical targets in the underlying layer are spot-faced and LDI is deployed and op- timized to define the over-lying layer features. Additional targets can be added for localized/ critical positional accuracy requirement. Figure 2 shows an image of a LCP MLB that deployed this technique. In terms of componentry, the mmW indus- try is benefiting from packaged devices (e.g., QFN and BGA). This is an evolving process. An example of packaging developed recently for the mmW industry is the embedded wafer level ball grid array (eWLB) package, developed and used by Infineon Technologies [5]. These pack- aged components are available up to 86 GHz (BGT80). Flip-chipping of MMIC dies is also a promising technology for high performance mmW interconnects. Flip-chip bumps or pil- lars are typically less than 100 µm in height and have low parasitic inductance. However, there are problems with flip-chipped high-power circuits due to thermal issues. A multitude of bumps would need to be dedicated for thermal transfer from the die to PCB. For some MMIC Figure 2: X-ray image of laser-drilled plated via in sequentially laminated LCP MLB located using localized optical alignment and LDI.