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52 The PCB Design Magazine • April 2017 is readily achieved with a continuous ground reference plane, but becomes increasingly dif- ficult with the addition of more and more plane layers on a multilayer PCB. A ground plane serves well as a signal return, provided the ground is continuous under the signal path. But even with a continuous return path, there may be enough voltage drop across the plane to generate a common-mode voltage. And if left unchecked, may escape as electromagnetic emissions via the signal or power/ground con- ductors. RPDs have a huge impact on supply bounce of single-ended signals. Fortunately, differential signaling dramatically reduces this affect. Serial interfaces also significantly reduce the number of interconnects, which is anoth- er advantage over the use of parallel buses for high-speed design. Small discontinuities, such as vias and non- uniform return paths on a bus, are becoming important factors for the signal integrity and timing of high-speed systems. RPDs produce impedance discontinuities due to the local re- turn inductance and capacitive changes. Im- pedance discontinuities create reflected noise, contribute to differential channel-to-channel noise and may promote mode conversion. In the case of differential pairs, the transformation from differential-mode to common-mode typi- cally takes place on bends and non-symmetrical routing, near via and pin obstructions, but can also be caused by small changes in impedance due to RPDs. RPDs also impact on power integrity be- cause of the impedance shift in the PDN. Dif- ferent techniques must be adopted in order to minimize problems such as ground bounce noise and parallel plate waveguide resonances in multilayer PCB planes. Furthermore, RPDs tend to cause timing push-outs. A timing push-out (or expansion) is an increase in the flight time of a signal com- pared to an ideal interconnect. Often seen as a ledge in the rising/falling edge or a diminished rise time at the receiver, these push-outs con- sume valuable timing budgets allocated to the designer. Any type of non-ideal return path will introduce additional timing uncertainties, into the system, which degrade timing budgets and signal integrity. Therefore, the ability to iden- tify the specific mechanisms that contribute to the performance degradations is essential to a good design methodology. In the case of a split in the reference plane, the most disruptive effect is a significant induc- tive spike as seen in Figure 1. This plot compares a 25 and 100 mil gap in the return plane. This disruption is caused by the increase in current loop area which corresponds to an increase in inductance following the relationship: Where L is the inductance, Φ is the flux defined by the magnetic field, and the area between the trace and plane, and I is the loop current. As the gap forces the return current to diverge, the flux loop defined but the signal trace current and plane current increases, thus increasing the inductance. This spike can pose a serious problem since it will degrade the sig- nal integrity at the receiver, filter the edge rate and increase inter-symbol interference. If this degradation is severe enough, it may cause a false trigger at the receiver or extend the timing enough to violate the setup and hold times. But most importantly, RPDs typically mani- fest themselves as intermittent operation and degrade the performance of the product which can be extremely difficult to debug. RETURN PATH DISCONTINUITIES Figure 1: Inductive spike for 25 & 100 mil gaps (source: Byers).