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54 The PCB Design Magazine • June 2017 FPGA PCB DESIGN CHALLENGES devices from Altera, Lattice, Microsemi, and Xilinx. Therefore, you may use the same HDL design source files and constraints to target any device and to obtain a synthesized netlist that can be used for place and route with the appro- priate vendor tools. This vendor independence, allows users to easily retarget and analyze re- sults for any FPGA device, enabling you to find the best FPGA device to suit the design. Until recently, the FPGA-PCB I/O optimiza- tion tools were expensive and only available with enterprise level flows such as Cadence Al- legro and Mentor Xpedition, but are now also an affordable option to the PADS Professional suite of PCB design tools. Automating the error- prone boundary between FPGA and PCB design makes sense. Design teams need to implement new methodologies to ensure they do not ne- gate the cost and time-to-market benefits of us- ing programmable logic in the first place. Points to remember: • The added complexity of FPGA integration has introduced many PCB layout challenges. • EDA design tools have not kept pace with the growth in FPGAs. • The primary issue is generating optimal FPGA pin assignments that do not add vias and signal layers to a PCB. • FPGA I/O assignment is in a constant state of flux. • Cross-overs of the rat's nest should be minimized to give the router the best possible chance of completion. • The problem now is how to back anno- tate this modified FPGA pin assignment to the FPGA design tools. • The manual process is time consuming, te- dious and error prone. • The key issue is to ensure consistency be- tween the tool sets used in the FPGA and PCB environments. • Using the right tools can provide parallel paths of FPGA and PCB design, trimming weeks from the design process and implementation schedules. • Schematic, PCB layout and FPGA databases should always be synchronized which provides user control of the project's design data flow. • An FPGA vendor neutral design environ- ment, which enables architecture-specific op- timization, takes advantage of the specific fea- tures for each FPGA device. PCBDESIGN References 1. Barry Olney's Beyond Design columns: Rise of the Independent Engineer. 2. "FPGA I/O Features Help Lower Overall PCB Costs," by Dave Brady, Mentor Graphics. 3. I/O Optimization: Mentor Graphics, PADS literature. 4. FPGA-PCB Co-Design Option for PADS Professional: Mentor Graphics, PADS literature. Barry Olney is managing director of In-Circuit Design Pty Ltd (iCD), Australia, a PCB design service bureau that specializes in board- level simulation. The company de- veloped the iCD Design Integrity software incorporating the iCD Stackup, PDN and CPW Planner, available for download at In a paper published today in Advanced Ma- terials, corresponding author Orlin Velev and colleagues show that, in a water medium, liq- uid silicone rubber can be used to form bridges between tiny silicone rubber beads to link them together – much as a small amount of water can shape sand particles into sandcastles. "There is great interest in 3D printing of sili- cone rubber, or PDMS, which has a number of useful properties," said Velev, INVISTA Professor of Chemical and Biomolecular Engineering at NC State. "The challenge is that you generally need to rapidly heat the material or use special chemistry to cure it, which can be technically complex." New Technique Enables 3D Printing with Paste of Silicone Particles in Water

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