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52 SMT Magazine • September 2017 desiring thinner phones with longer battery life and increased sensor functionality. High- density and stacked PCB designs, system in package (SiP) assemblies, and small form fac- tor packages have all emerged as solutions for sleeker styles and improved functionality. In particular, WLPs are gaining popularity for their low cost, small footprint, and thin profile. The newest smartphone models contain an aver- age of 5-7 WLPs, with many WLPs used as RF transceivers, power management units, audio amplifiers, and BlueTooth and GPS modules [1] . Unlike traditional packages, WLPs are pack- aged and bumped first, then diced. Passivation and dielectric layers are added to the die fron- tside, followed by metallic redistribution lay- ers. A second dielectric layer is deposited, then the underbump metallization and solder balls are attached. Lastly, the packages are singulated from the wafer. Figure 1 illustrates the two dif- ferent categories of WLPs: the traditional a) fan- in WLP, and the newer b) fan-out WLP. The di- electric is exposed on the edges and frontside of fan-in WLPs, while the silicon backside is of- ten covered with a protection tape. As the name suggests, fan-out WLPs "fan out" interconnects from the smaller silicon die to the larger pack- age dimensions. The fan-out design allows for ball pitch customization, higher I/O density, and easy integration with SiPs and other multi- die packages. The board-level reliability is also improved by protecting the silicon die with an epoxy mold compound. Though WLPs offer considerable advantag- es, they also pose challenges for failure analy- sis—particularly when reball and component- level testing are required. Figure 2 illustrates the typical FA process flow for a failing system, such as a mobile phone, tablet, or wearable de- vice. Fault isolation is performed first to iden- tify the failing component, then nondestruc- tive FA is used to inspect for failures at both the board- and package-level. If the failure is subtle or cannot be found non-destructively, the pack- age must be reworked and reballed before pro- ceeding with socketed component-level testing REWORK AND REBALL CHALLENGES FOR WAFER-LEVEL PACKAGES Figure 1: Cross-section schematics of (a) a traditional fan-in wafer level package, and (b) a newer fan-out wafer level package.

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