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62 SMT Magazine • September 2017 2. Y. Li, P.K.M Srinath, D. Goyal, "A Review of Failure Analysis Methods for Advanced 3D Microelectronic Packages," Journal of Electron- ic Materials, January 2016, 116-124. 3. A. Wilson, "IR Cameras Tackle PCB In- spection Applications," 2007. 4. M. Pacheco, "Detection and Character- ization of Defects in Microelectronic Packag- es and Boards by Means of High-Resolution X- ray Computed Tomography," IEEE Electronic Components and Technology Conference, June 2011, 1263-1268. 5. A.A. Primavera, "Process Issues for Fine- Pitch CSP Rework and Site Scavenging," Etron- iX Conference Proceedings, 2001. 6. J. Wade, R. Aspandiar, D. Naugler, T. Lea- hy, "PCB Pad Site Dress Methods on BGA and Socket Pad Arrays," SMTAi Conference, 2010. Acknowledgements The authors would like to thank the teams from the Global Platform Analysis Center (GPAC) and Assembly and Test Technology De- velopment (ATTD) FA Labs. Editor's Note: This article was originally pub- lished in the proceedings of SMTA International. Lauren Cummings is a failure analysis engineer at Intel Corp. Priyanka Dobriyal, Ph.D., is a data center execution engineer at Intel Corp. REWORK AND REBALL CHALLENGES FOR WAFER-LEVEL PACKAGES Figure 14: Representative optical images (a and b) showing chipping near the dielectric and top layer metallization. Table 1: Summary of challenges and risks associated with each rework step, along with the implemented solution.