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50 The PCB Magazine • October 2017 pacitors is the trace-via combination to power and ground. By placing the microvia in the SMT pad, this inductance is decreased to practical- ly nothing. This is compared to a conventional trace to a through-hole that at 20 mils would be as much as 500pH to the loop inductance. This loop difference is shown in Figure 7. Using a via-in-pad microvia and a surface ground plane, there is essentially no induc- tance to ground, and if power is used as the sec- ond layer under the microvia, only a minimum inductance to power. The close nature of this power/ground combination will lower loop in- ductance and provide a significant amount of decoupling capacitance. A final advantage is the reduction of part spacing and a shortening of all the signal tracks. Figure 8a and Figure 8b show high-speed controlled impedance multi- layer redesigned with only the use of microvias- in-pads [5] . No parts were changed and current assembly minimum spacing was observed. The advantages from a cost and size point-of-view is nearly 40% lower cost, from 12 layers to eight layers, and 40% smaller in size, allowing more up on a fabrication panel. The signal integrity was improved significantly. Note that Figure 8a shows a 12-layer, con- trolled impedance multilayer that was rede- signed employing only microvia-in-SMT pads. The original through-hole version is shown on the left side of the figure, and the microvia ver- sion requiring only eight layers is shown on the right side. Also note that Figure 8b shows the secondary side of the redesigned multiplayer, il- lustrating the advantage of blind vias and the via-in-pads design concept. Power/Ground Distribution Keeping the inductance of the power and ground distribution low is a major objective if fast rise-time circuits are going to be used. Two factors that contribute to the inductance of the power and ground interconnect are the phys- ical length of the path and the separation be- tween the actual power and ground planes. Again, Bogatin's advice [3] is, "The use of very thin dielectric layers between the power and ground planes contributes to a very low loop inductance for the power and ground currents. For two rectangular conductor sheets, separated by a dielectric thickness, h, the loop inductance for current to go down one surface and return back on the other is given by: "Where len is the length of the current path and W is the width. The loop inductance de- creases as the spacing between the power and HDI'S BENEFICIAL INFLUENCE ON HIGH-FREQUENCY SIGNAL INTEGRITY Figure 8a: Redesigned multilayer (component side). Figure 8b: Redesigned multilayer (circuit side).