Issue link: https://iconnect007.uberflip.com/i/886239
46 The PCB Design Magazine • October 2017 by Andy Shaughnessy I-Connect007 DDR5 is expected to double the memory bandwidth and density of DDR4. I recently spoke with SiSoft Chief Scientist Walter Katz about his company's efforts to hit the market with this game-changing technology in 2018. Andy Shaughnessy: I understand SiSoft is pre- paring for the upcoming DDR5 standard. What does this mean for the user? Walter Katz: DDR5 is expected to range from 3,200 million transfers/second (MT/s) to 6,400 MT/s. These high data rates, when combined with the discontinuities inherent in DDR5 sys- tem topologies, will cause significant Inter Sym- bol Interference (ISI). This ISI will require that active equalization techniques be used in both the controller and memory I/O buffers to recov- er a usable signal, similar to what we have seen in serial channels for some time now. JEDEC is setting the standard for the equalization used in the memory chips, while equalization methods for the controller will be determined indepen- dently by each controller manufacturer. So let's focus on the memory devices. Currently, there is no requirement for equalization on the mem- ory's driver (the memory read operation), while we expect to see a requirement for a four-tap de- cision feedback equalization (DFE) on the mem- ory's receiver for both DQ write and address/ command operations. A four-tap DFE adds (or subtracts) a voltage to the voltage at the receiv- er pad based on the values of the previous four symbols (bits) that have been received. There is also some consideration of including a peaking filter before the DFE in the memory's receiver; we'll have to wait and see how that plays out. Shaughnessy: We're hearing about AMI models being used to model DDR5 data transfers. Can you give a brief summary of how an AMI works? Katz: The IBIS-AMI, or AMI (Algorithmic Mod- eling Interface) was created in 2007 to help analyze high-speed SerDes (serialize/deserial- ize) channels. Today, those channels operate between 3 Gbps and 56 Gbps, and IBIS-AMI FEATURE INTERVIEW