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22 SMT Magazine • November 2017 by Andy Shaughnessy, Happy Holden, and Stephen Las Marias I-CONNECT007 Mike Creeden has been in the PCB design industry for more than 40 years. In June 2003, he founded San Diego PCB Inc., a design bu- reau serving a variety of industries, including industrial, automotive electronics, medical di- agnostics, defense, aerospace, and communica- tions markets. The company was acquired by EMS firm Milwaukee Electronics in November of 2016. Currently, Creeden is the vice presi- dent of layout services for San Diego PCB De- sign LLC, which has about 18 designers and supports four CAD platforms. He is also a mas- ter instructor at EPTAC, where he teaches CID+ certification classes across the country. San Diego PCB has designed a variety of HDI circuit boards over the years. So, for this month's issue of our magazines, we interviewed Creeden to get his insights on the challenges when it comes to HDI and how designers and manufacturers can address those issues. Typically, HDI can improve the performance for dense, high-speed signals. HDI may have lit- tle or no effect on design cycle time. However, HDI is usually a cost adder to the fabrication cy- cle, with some exceptions, such as layer reduc- tion. Most HDI issues are negligible to the PCB assembly process. "HDI, along with almost any aspect of PCB design layout, in my opinion, should consider three perspectives for success: layout solvabili- ty, whereby oftentimes there's a complex pack- aging challenge involving dense BGAs or fine- pitched BGAs that need pin-escapes; electrical integrity—including all signal and power integ- rity considerations; and DFX manufacturabil- ity," explains Creeden. "A designer must ap- proach HDI and any portion of PCB design lay- out with all three of those perspectives in mind. "The solvability is a skillset that a design- er would have to essentially understand and be competent to truly satisfy the placement and connectivity of the board with their CAD tool. HDI exists in many different forms. For exam- ple, via-in-pad. It would require half the geom- etry to pin-escape a board if you can put the via right in the pad. Therefore, you must consider FEATURE

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