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November 2017 • SMT Magazine 55 THE PROPER POSITION TO TAKE ON VOIDS IN SOLDER JOINTS, PART 1 cess translates to 3.4 DPMO (defects per million opportunities). And, in the real world most electronic as- sembly operations aim for 5-sigma (233 DPMO) or even a 4-sigma (6,210 DPMO) defect rate. If there are 1000 solder joints (opportunities) per board, there will be about six board failures per 1000 at 4-sigma and less than one board failing per 1000 at 5-sigma—even less board failures if more than one defect is found per board con- sidered. How much money are you willing to spend to wring out all but 3.4 in-process DPMO to at- tain 6-sigma? Of course, if the defects are ran- dom and not in the assignable cause category, no amount of money will identify their root cause. Since we began this Jumping Off the Band- wagon column, we have stressed the competi- tive importance of high assembly yields to re- duce labor content in high labor rate regions of the globe. And, with a first-pass in-circuit test (ICT) yield of 99.6% coupled with passing a functional test as the board's final acceptance (4 failures per 1000 boards or 4,000 DPMB (de - fects per million boards—assuming 1 defect per failed board), it makes sense to eliminate the ICT. The functional test will identify the defec- tive circuit boards. It doesn't pay back to sub- ject 4000 boards to ICT to find the four with defects. Let's start with this: The product team, whether they belong to an OPD or an EMS, should write a quality assurance plan (QAP) for each assembly. Unfortunately, today I find most people in the industry don't even know the dif- ference between quality assurance (QA) and quality control (QC). The QAP must clearly state what the accep- tance criteria is for voiding and the inspection plan that will be used to ensure this acceptance level is met. The plan may invoke industry stan- dards as well as company standard operating procedures (SOP) and any specific quality re- quirements such as inspection sampling plans, both automated and manual. In most cases the student who moves through the looking glass from the academic side to the real-world side has most likely never even heard the phrase "solder joint void." Is History Repeating Itself? A couple of firsthand experiences from the graveyard of forgotten favorites: 1. Do you remember tweakers? Before circuit board labor content became an issue (pre-low la- bor rate competition, circa 1983) and when com- ponent placement accuracy had significantly more variation than we have today, many board assembly lines stationed a tweaker(s) between the exit of the pick and place machine and entrance of the reflow oven. With tweezers in hand their job was to gentle center components that were not perfectly placed in the wet solder paste. So, if even one component was tweaked per board the true first pass yield was zero. This reactive process caused much unnecessary rework to be done. This is the risk with how we approach sol - der joint voids. However, the risk is much more serious and costly since it in post reflow rework. 2. I remember the beginning of the commer- cial use of SMT. Assembly processes were being refined and there was significant process un- certainty accompanying the use of these com- ponents—components that weren't anchored to the PCB with a lead that went through the board with a plated-through barrel full of sol- der. This caused a cautious approach in permit- ting the use of this new technology in the mil- itary. The Air Force was seduced by the lighter weight. However, they needed to be persuaded that the use of SMT in their electronic equip- ment was at least as good as the traditional pin- in-hole (PIH) technology and did not reduce the reliability of the system. When an aircraft testing the technology had its navigational system fail in flight, the flags " This is the risk with how we approach solder joint voids. However, the risk is much more serious and costly since it in post reflow rework. "