Issue link: https://iconnect007.uberflip.com/i/895789
26 SMT Magazine • November 2017 of the BGA. This will dictate if any sort of via grid is required. If microvias are required, now I have taken myself into an HDI scenario. Fi- nally, when you look at a large BGA, you often- times see how many signal pins that need to pin-escape. The amount of signal pins that may need to pin-escape a large BGA may constrain how many layers will go into a stack-up. Third, I will collaborate with my production fabrica- tor to ensure complete high-yield buildability. With these three things, I can typically give you an estimation for feasibility at the beginning of the layout phase. Designers need to talk to their full development team and complete supply chain before they go and layout the boards. It's all about being proactive, not reactive." Testing Issues Every circuit has different testing require- ments or desires, depending on customer re- quirements, production plan, or end use. Sev- eral methods for testing in the should be given careful consideration depending on what best suits your situation. Different testing methodol- ogies have varied strength and weaknesses. "From a layout perspective JTAG testing can be one of the simplest to implement," says Creeden. "Some companies would like to have ICT. It's expensive, but way more defini- tive as to the condition of the manufactured board. But you need full nodal access with ICT fixtures. When I have BGA pins that use mi- crovias such as blind and buried, you do not have accessibility unless you can breach it to the outer surface. Then you might be violat- ing the electrical integrity. And more than like- THREE PERSPECTIVES ON HDI DESIGN AND MANUFACTURING SUCCESS they do a lot of testing; IST and HATS testing, are a couple of methods. However, if it's done on a coupon, you always have to ask if that coupon truly reflects the circuit as it's laid out. These designers can theorize the stack-up, but if they violate it, with the way they actually did the design, the coupons are really not represen- tative. An asymmetrical stack-up is a good ex- ample of this occurrence, whereby the designer routes signals broadside coupled and not asym- metrical. The amount of cycles by which you test these vias in coupons—some people say 250 cycles at a certain temperature and some re- ports actually suggest 500 cycles—a person who wants to rely on these different testing methods should really investigate them to see where the sweet spot is, and if that fits with their budget and margin." Designers have always been asked to esti- mate the scope of schedule, performance prob- ability and then provide technical feasibility for cost estimates and planning. On this, Creeden says, "I must do an estimation of this design; and typically, I can tell you early on if it's feasi- ble and the scope. The first thing I want when estimating the scope is placement feasibility and assembly profile. I consider the placements of components to see if I can fit these compo- nents on the space provided—I do a compo- nent dispersant, where I just dump them all out on a board; at this point I don't care about the circuit flow—I just want to see wall-to-wall if I can put parts on the board. Because if I can, I could always do a via-in-pad, and I can go un- derground and solve the routing. The second thing I need to look at is the smallest pin pitch Figure 4: Never stack microvias on resin-filled vias.