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November 2017 • The PCB Magazine 23 but the biggest) still presents an issue and that is electrical testing. Contacting fine pitch devices is still a problem for the bare substrates as well as the populated assembly. HDI Assemblies If you think high-density bare substrate test- ing is difficult, it is nothing compared to testing the populated substrate. Two of the HDI driv- ing forces are area array packages and via-in- pad. When used on a HDI assembly, just these two eliminate the normal via breakout pattern that assembly level testing uses for probing. As- sembly level testing for HDI assemblies must be considered and a solution provided while the product is being created and designed. This is now called design for test (DFT) and many CAE/ CAD software systems are beginning to provide this function. For large OEMs and companies that can design their own integrated circuits, limited access peripheral testing can be used like boundary scan or built-in-self-test (BIST). For the rest that create their product from stan- dard ICs, other testing options will have to be considered. Sub-Panel Testing One of two innovative ways to test HDI as- semblies is to put the test points external to the assembly, in the carrier sub-panel. This is best il - lustrated by the Figure 7. You will notice that, after assembly and assembly test, if the circuit is per- forming correctly, it is excised out of its carrier. This is also the technique used to electroplate pure gold on the bonding pads of BGAs. The excis- ing can be break-away, punched or routed. Embedded Test Structure On one HDI design project I was involved in, the final assembly was a 4-layer IPC Type II Structure (1+2+1). It was a high-volume module for portable computers and could be tested after assembly with just limited access to peripheral I/O con- nections. Since it employed fine-pitch BGAs and via-in-pad wiring, the various data busses and data streams could not be accessed from the surface. In this case, we designed two additional, redundant build-up layers over the existing four layers to provide data access and troubleshooting. The resulting 6-layer HDI substrate (2+2+2) was only used for prototyping and initial production ramp. Once assembly and test diagnostics stabi - lized, the two outer, redundant test HDI lay- ers were removed and only the 4-layer HDI structure was continued. Today, if you were to reverse engineer this module, it would be impossible to figure out how it had been de - veloped. Figure 8 shows a cross-section of the six-layer HDI structure with the two test lay- ers applied. Electrical testing will try our patience. But when it is all over and we will finally have our cost-effective solution, I'm sure that it will also provide us with a new testing technolo- gy, including design for test and overall lower test costs in general. Figure 7: Test contacts designed to be external to the board. (Source: Dyconex) 35 YEARS OF HDI FABRICATION PROCESSES AND OBSTACLES FOR IMPLEMENTATION