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38 The PCB Magazine • November 2017 however, the drill bit selected to furnish a fin- ished hole size of 200 μm (8 mil) diameter will be more practical, less prone to breakage and, because they can be sharpened, facilitate a lon- ger life. Laser Ablation When a circuit board design requires hole di- ameters smaller than 150 μm (6 mils), fabricators will generally adopt the CO 2 laser ablation pro- cess to form the vias, however, alternative laser technologies may be employed to initially ab- late the copper foil. There are five common vari- ations of laser-ablated and plated vias: through- via, blind via, buried via, stacked via and stag- gered via. Laser-ablated and plated through-via holes are used for general interconnect applica- tions that connect conductors on the outer sur- faces of the board as well as connecting to lay- ers within the multiple layer circuit structure. In addition to through-via applications, laser- ablated and plated blind vias will furnish inter- connect from either outer surfaces of the board to conductors on designated innerlayers. These vias may be placed in lands that are only slight- ly larger than the initial via diameter. Design- ers can also position the plated blind via within the component's land pattern geometry; how- ever, these via holes must be specified as 'plat- ed closed' and flush with the outer copper sur- face of the board. This is because any remaining depression within the land pattern's surface can result in void propagation with the solder inter- face, especially a concern for array-configured components. The buried via may be mechanically drilled or laser-ablated on one or more inner or core layers of the multilayer board structure. These vias will be specified as plated and filled prior to the lamination of additional build-up lay- ers. Multilayer boards can be designed using vertically stacked via processing. This process is used for more complex structures requiring circuit layers to be processed and laminated se- quentially, ablating and plating vias in the cop- per foil and chemically etching the circuit fea- tures before laminating the next layer. A varia- tion of the stacked via process is the staggered via where via lands are slightly offset from one layer to another. A key issue is the aspect ratio of via diame- ter to the overall thickness of the copper and di- electric. Via diameter to land diameter ratio re- quirements may differ from one supplier to an- other but the following table may be referenced as a base for discussion (Table 2). Regarding stacked vs. staggered via reliabil- ity, some experts acknowledge that, although the small layer-to-layer interconnecting vias will furnish a robust interconnect solution, stacked vias are said to be less robust than the staggered via alternative. As always, the design- er is advised to establish dialog with the PCB fabricator early in the design stage of the pro- gram. They will be the designers' best source re- garding guidance in material selection and fab- rication process planning. PCB Vern Solberg is a technical consultant specializing in surface mount technology and microelec- tronics. He has served the industry for more than 30 years in areas related to both commercial and aerospace electronic product development and holds several U.S. patents for 3D semiconductor packaging innovations. To read past columns or to contact Solberg, click here. STRATEGIES FOR HIGH-DENSITY PCBS Table 2: Via diameter to land diameter ratio variations.