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November 2017 • The PCB Design Magazine 25 Figure 3: Example of HDI microvias accessing buried planar capacitance layers for robust power delivery. is stack them on top of what's known as the 'N' or the internal mechanical drilled via, because it is always best if the mechanical drilled via is non-conductive resin filled. There are thermal expansion issues at play that create via failures. You'd see that if you look at a lot of microsec- tions; you can see that the non-conductive fill actually retracts a little bit because it has a ther- mal shield being inside the via wall. So, if you stack vias on top of it, essentially you have a much greater potential of having an open via failure. "Typically, the limit of how many microvias can be stacked is a consideration of the number of lamination heat cycles the FR-4 material can withstand, and that number is debatably about four to five. I'm sure higher-end shops may be exceeding this at some point, but the limit is the material. Other methods of stacking vias on every layer is utilized in the telecom for tablets and cellphones that are typically thin boards. This method has been called by names like: full-stack-vias, every-layer-vias, or any-layer-via. They utilize a CU-sintered conductive paste as opposed to conventional plating methods. To this end, always keep an eye out for new meth- ods coming around the bend." While laser-drilled vias are reliable, they still present a lot of fabrication challenges. "Under- standing some of the manufacturing process that your fabricator has to work with, I always encourage people that if you want to design a stack-up, the fabricator needs to weigh in. You don't create a stack-up, then route your board, and then after that, ask for the fabricator for a DFM review. You truly need to theorize your stack-up and all the feature sizes that you need for the layout solvability, such as pin-escapes, smallest features, and overall routing comple- tion; you must ensure that you satisfy the elec- trical integrity such as impedance and imple- menting proper EM theory. Then, get your DFM review at the start of layout to make sure this can be built. You do not ask those questions after you routed the board. I repeat: Ask those questions at the start of the design. Considering manufacturability, it's much more of a fabrica- tion issue than it is an assembly issue. Fabrica- tors will provide conformance certificates, and they do a lot of testing; IST and HATS testing, don't kid yourselves. But it has very good per- formance. When you have no room for decou- pling capacitors, then you may be forced to use it. Or if you work for someone like NASA or the military—maybe you're not as cost-sensitive—I recommend people consider it because it works well with HDI and improves performance." However, there are sometimes tradeoffs when it comes to pin escape and power deliv- ery. And therein lies the challenge brought by the number of pins in the BGA. "Whenever pos- sible, in HDI, if you can bring your connectivity underground (layer 2), and I mean under 0.0V GND, you have EMI containment. Thus, it is easier to pass any kind of FCC or emissions test- ing that your product may encounter. When- ever a signal is encapsulated by ground layers, with adjacent return paths, you have good con- tainment of its EM field, so they'll perform bet- ter, and you'll reduce noise emissions and sus- ceptibility." While there are a lot of signal integrity tools that try to help designers detect EMI noise, Creeden says he always encourages PCB design- ers to "make the EMC correct by construction and not create noise, rather than detect it." "Another caveat that I would always recom- mend from a manufacturing standpoint when dealing with microvias is the concept of stacked or staggered vias. It's a methodology by which when you're utilizing microvias to traverse multiple layers, you may stack them on top of each other or stagger them, offsetting them so they're not on top of one another. When you stack a laser via on top of a laser via, they will typically end up metal-filling that. It's okay be- cause they have a thin dielectric, and there's less stress on the via. But what you should never do THREE PERSPECTIVES ON HDI DESIGN AND MANUFACTURING SUCCESS

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