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32 The PCB Design Magazine • November 2017 decoupling capacitors consist of both inherent and mounting parasitics. The inherent parasit- ics, effective series resistance (ESR) and effec- tive series inductance (ESL), are properties of the capacitors themselves. The mounting of the capacitors can add significant inductance and resistance, and minimizing those mount- ed parasitics maximize the effective frequency range of the capacitor. The most effective means of doing so is by minimizing the loop area of the connection of the capacitor between pow- er and ground. This means placing mounting vias as close together as possible, and placing the capacitor as close as possible to power and ground. It is clear how HDI aids in accomplish- ing this; by allowing placement of connection vias within the capacitor pads, they are as close together as possible. Power Integrity and HDI Common to all methods of HDI is a signifi- cant reduction in the numbers of vias going through the inner layers of the board. The main desired by-product of this is the increase in board real estate available for routing. Also evi- dent is the reduction in perforation of the pow- er planes by the large number of anti-pads nor- mally present in a chip pin-out. This results in a greater area of copper used to feed both AC and DC current to the chip power pins. There is less resistance in the current path, both to the chip and throughout the plane in general, result- ing in less areas of high current density on the board. There is also less inductance leading to the chip pins, allowing for appropriate switch- ing currents to reach the power pins, while also increasing the effectiveness of the decoupling capacitors surrounding the IC. The effectiveness of the decoupling capaci- tors is also affected by the location of the power and ground planes within the board stack-up. The power and ground locations are determined by the type of HDI being used. In all cases the planes will sit more towards the outer layers of the board, but the mounted inductance of the decoupling capacitors will vary based upon whether or not the planes are adjacent, and where they sit in the stack-up. This effect is evi- dent even on a single decoupling capacitor, but becomes even more exaggerated when an entire power distribution system is viewed. Another significant effect of power and ground plane configurations is the change in the contribution of plane capacitance to the overall power distribution network impedance. Inher- ent to the use of HDI technologies are thinner dielectric materials, which increase the embed- ded capacitance in power-ground plane pairs. Very specific thin, high-dielectric constant ma- terials may be used for creating embedded ca- pacitance, but even the dielectrics typically used for microvias will exhibit similar characteristics. Plane Perforation Often the primary motivator for utilizing HDI technology is the presence of fine-pitch BGAs on the PCB. When pin pitches approach 0.65 and 0.5 mm, it becomes impossible to route signal traces out of the BGA using conventional via technology. Via pads would be so large they would choke out any room for routing between pins, and could even overlap. Additionally, the via anti-pads would overlap and eliminate the presence of any ground or power plane within the PCB. The narrow web of copper formed by closely-spaced anti-pads, especially in BGA pin- fields, can be a major weak point for the PDN, and can cause serious problems at DC. One of the advantages of HDI is the ability to use blind vias to connect IC pins only to the layers they need. This eliminates extra anti-pads on plane layers and can substantially increase the amount of copper feeding the IC power pins. For example, removing all the ground vias from the area of the power plane in a BGA pinfield re- sults in dramatically improved DC power deliv- ery. If ground pin anti-pads are eliminated from the power plane, and the remaining power pin " Common to all methods of HDI is a significant reduction in the numbers of vias going through the inner layers of the board. " THE IMPACT OF HDI ON PCB POWER DISTRIBUTION