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November 2017 • The PCB Design Magazine 49 hole size of 200 μm (8 mil) diameter will be more practical, less prone to breakage and, because they can be sharpened, facilitate a longer life. Laser Ablation When a circuit board design requires hole diameters smaller than 150 μm (6 mils), fabricators will generally adopt the CO 2 laser ablation process to form the vias, however, al- ternative laser technologies may be employed to initially ablate the copper foil. There are five common variations of laser-ablated and plated vias: through-via, blind via, buried via, stacked via and staggered via. Laser-ablated and plated through-via holes are used for general intercon- nect applications that connect conductors on the outer surfaces of the board as well as con- necting to layers within the multiple layer cir- cuit structure. In addition to through-via appli- cations, laser-ablated and plated blind vias will furnish interconnect from either outer surfaces of the board to conductors on designated inner- layers. These vias may be placed in lands that are only slightly larger than the initial via di- ameter. Designers can also position the plated blind via within the component's land pattern geometry; however, these via holes must be specified as 'plated closed' and flush with the outer copper surface of the board. This is be- cause any remaining depression within the land pattern's surface can result in void propagation with the solder interface, especially a concern for array-configured components. The buried via may be mechanically drilled or laser-ablated on one or more inner or core layers of the multilayer board structure. These vias will be specified as plated and filled prior to the lamination of additional build-up layers. Multilayer boards can be designed using verti- cally stacked via processing. This process is used for more complex structures requiring circuit layers to be processed and laminated sequen- tially, ablating and plating vias in the copper foil and chemically etching the circuit features before laminating the next layer. A variation of the stacked via process is the staggered via where via lands are slightly offset from one lay- er to another. A key issue is the aspect ratio of via diam- eter to the overall thickness of the copper and dielectric. Via diameter to land diameter ratio requirements may differ from one supplier to another but the following table may be refer- enced as a base for discussion (Table 2). Regarding stacked vs. staggered via reliabil- ity, some experts acknowledge that, although the small layer-to-layer interconnecting vias will furnish a robust interconnect solution, stacked vias are said to be less robust than the staggered via alternative. As always, the designer is advised to establish dialog with the PCB fab- ricator early in the design stage of the program. They will be the designers' best source regarding guidance in material selection and fabrication process planning. PCBDESIGN Vern Solberg is a technical consultant specializing in surface mount technology and microelec- tronics. He has served the industry for more than 30 years in areas related to both commercial and aerospace electronic product development and holds several U.S. patents for 3D semiconductor packaging innovations. To read past columns or to contact Solberg, click here. STRATEGIES FOR HIGH-DENSITY PCBS Table 2: Via diameter to land diameter ratio variations.

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