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36 The PCB Design Magazine • December 2017 dielectric layers depends on the thickness of copper either side to allow for the difference in the coefficient for thermal expansion [8] , which gives the total thickness of the board. For small, high-power, low-pin-count pack- ages, the length scale of traces on the board are a similar order of magnitude to the package. Model these features in a similar level of geo- metric detail to the package before this infor- mation is available from the electronic design automation (EDA) system. For example, you can represent the copper pad that a TO pack- age is soldered to, and traces local to the pack- age, when the package is modeled in detail. The same applies to modeling any thermal vias below the pad used to conduct heat down to a buried ground plane. Once you get down to this level of detail, the thermal simulations are highly accurate (Figure 3). Import Data from the Design System Importing component placement data from the EDA system ensures that placement within the thermal tool is correct, and you should reim- port it whenever the layout is changed. Detailed PCB modeling involves importing the stackup, the routing of trace layers from the EDA system, the distribution of vias, and the copper shapes on power and ground planes. When thermal design from a mechanical perspective is done in parallel with the thermal design from an electrical perspective, the ther- mal design aspects of the board can close faster, more reliably, and with a better outcome than if it is undertaken in only one flow. Key to this is a shared understanding of what work can and should be done in each flow and how they can interact with, and affect, each other. PCBDESIGN References 1. "12 Key Considerations in Enclosure Ther- mal Design… A High-Level 'How To' Guide," Mentor white paper. 2. Tony Kordyban (1994) "Estimating the Influence of PCB and Component Thermal Conductivity on Component Temperatures in Natural Convection," Third International FloTHERM User Conference, September 1994, Guildford UK. 3. Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board. JEDEC JESD51-8, October 1999. 4. Transient Dual Interface Test Method for the Measurement of the Thermal Resistance Junction to Case of Semiconductor Devices with Heat Flow through a Single Path. JEDEC Standard JESD51-14, November 2010. 5. Two-Resistor Compact Thermal Model Guideline. JEDEC Guideline JESD15-3, July 2008. 6. DELPHI Compact Thermal Model Guide- line. JEDEC Guideline JESD15-4, October 2008. 7. Definition of PCB 7. Copper thickness FAQ John Parry is the electronics industry manager, mechanical analysis, at Mentor. He holds a PhD in chemical engineering. STREAMLINING THERMAL DESIGN OF PCBS Figure 3: Thermal simulation modeling result (top), compared with a PCB measured using an IR camera (bottom).

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