Issue link: https://iconnect007.uberflip.com/i/929192
92 DESIGN007 MAGAZINE I JANUARY 2018 There may be hundreds of such outputs on an IC, which all simultaneously impart switching noise onto the planes. The opposite applies to VDD bounce; when the output switch pulls the output voltage high (V OH ), the current surges through L VDD to the load. Supply bounce gets worse as a result of the following conditions due to the increased cur- rent drawn from the PDN: 1. Capacitive load increases 2. Load resistance decreases 3. Lead and trace inductance increases 4. Multiple gates switch simultaneously At high-speeds, the lead inductance of an IC package is critical. Larger packages tend to have more lead inductance. Wire bond, tape automated bonding (TAB) and flip-chip IC packages dramatically reduce the internal inductance by shortening the supply lead con- nections between the IC die substrate and the PCB planes. Fortunately for PCB designers, there are a number of approaches that can be imple- mented, particularly during layout and rout- ing of the PCB, to minimize the voltage drop, hence supply bounce, in the power delivery path: 1. Decrease the rate of change in the loop. Where possible, slow down the edge rates by employing series terminations. Also, some ICs now have clock skew adjustment to slow down the edge rate in addition to on-die terminations which are used to alleviate the need for exter- nal terminations. 2. Decrease the total loop inductance of the return path. Make the return path as short and wide as possible. 3. Bring the signal and return path closer together. This increases coupling and ensures that the return path follows the signal with a minimum loop area. 4. Limit the number of signals that share the same return path. A separate ground and VDD connection should be provide for each IC pin, directly connected to the ground or power plane, during the fanout routing of the pack- age. Connecting two or more pins together, and then routing them through the same trace to a common grounding via, defeats the purpose of multiple ground and power pins. 5. Minimize the inductance of the planes during layout by using wide plane pours rather than thick traces. 6. Use thin (<5mil) dielectric core materials between the power and ground planes. Or bet- ter still, use embedded planar capacitance to provide additional low inductance decoupling to the IC. 7. Optimize the power distribution network by analyzing the decoupling requirements across the entire frequency bandwidth. Low AC Impedance reduces radiation. 8. Locate power and ground vias adjacent to each other, where possible, so that the mag- netic flux is cancelled which minimizes com- mon-mode currents. 9. Preferably, select IC packages that have a large central grounding pad under the package and connect it using multiple vias to reduce the inductance to ground. Also, select a pack- age that has a high ratio of ground and power pins compared to signal pins. BGAs generally provide this but other SMT packages have lim- ited supply pins. 10. Choose an IC with the lowest drive cur- rent output that will provide the required per- formance. This reduces the amount of current available to rapidly charge the system capaci- tance, directly reducing ground bounce. 11. Stagger the timing of output pins on a device. Spreading the switching time of many outputs over an extended period can substan- tially reduce ground bounce at the IC level. 12. Use differential signaling and avoid com- mon-mode currents. Differential-mode is con- verted to common-mode at any imbalance in the pair. So it is best to correct any disparity as soon as it occurs by adding extra length, hence delay. Supply bounce cannot be eliminated and problems occur when its combined amplitude becomes excessive. However, low inductance and low AC impedance of the power distribu-