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60 DESIGN007 MAGAZINE I APRIL 2018 assembly, test or production processes. This is particularly true with complex, high-speed designs that have multiple planes and return paths, requiring elaborate constraints on every class of technology. Sure, we can enter hundreds of rules to constrain copper pours, placement and routing, but there is always some manual adjustment that needs to be made as each design is different and has spe- cific requirements. Online DRCs in EDA tools are a great safeguard, but they do slow the design process somewhat. They warn you when a physical or electrical rule is violated and allow the designer to steer clear of com- mon obstacles. Although the complete list of design rules is very broad, one must manage the following constraints at a minimum: • Placement • Clearance • Routing • High-speed signals–impedance and differential pairs • Plane and copper pours • Test points (if required) • Manufacturing Impedance discontinuities and crosstalk can be controlled to some extent by PCB design- ers during the routing phase if they understand these concepts, which many, unfortunately, do not. Although pre-layout analysis detects issues before they occur, signal integrity, power integ- rity and EMC issues cannot be properly evalu- ated until the design has been completed and a post-layout analysis is implemented. For instance, the most common cause of radiation from a multilayer PCB is a devia- tion or break in the return current path of a signal as in Figure 1. Electromagnetic fields couple the signal trace to the reference plane(s), and a gap in the return path will increase the loop area which typically causes radiated emissions. Nets crossing split planes can be examined manually but it is a very error-prone process particularly when there are multiple power supplies on multiple lay - ers. Additionally, the gap in the plane area or the break in the return path may not neces- sarily be in the nearest stackup layer. If poorly designed, the return path may be in a faraway layer. Many independent designers find it difficult to check their own work. They become blind to crucial design details. When you assess your own work, your brain already knows your intention and subconsciously skips the detail. Critiquing someone else's work is much easier because looking through another's eyes brings a fresh perspective. What is needed is a totally unbiased, automated check that considers only the established high-speed design rules. This is where HyperLynx DRC can comple- ment your EDA layout tools. It specifically scans for violations of signal integrity, power integrity and EMI rules. And, let's face it, these Figure 2: Available import formats to HyperLynx DRC.