30 DESIGN007 MAGAZINE I MAY 2018
two NRZ signals at 28GBaud are injected to
voltage-controlled voltage source to generate
a PAM-4 signal at 56Gbps. Simulation models
of PCB traces, break out vias, transmitter IC
package and receiver IC package are lumped
in the full path transmission line. At the trans-
mitting end, the signal amplitude and rise/fall
time are 1.2Vpp and 16ps respectively. The
PAM-4 eye diagram in Figure 11 has three eyes
due to its four digital amplitude levels. Deci-
sion feedback equalization (DFE) at receiver is
enabled. The channel simulation yields 90mV
eye height and 15ps eye width. The results
have to meet the specification in
[20]
before PCB
prototyping for actual physical layer compli-
ance test in
[21]
.
Conclusion
All the essential pre-layout effort discussed
in this article should be taken seriously in
designing PAM-4 PHY channels on PCB,
including material selection, transmission line
design and channel simulation. It is important
to implement the 56Gbps PAM-4 PHY link in
a stringent manner to guarantee a robust and
seamless communication between the high-
speed transceivers, paving the way for reliable
400GbE.
DESIGN007
References
1. The 2015 Ethernet Roadmap.
2. Baseline Proposal for
CDAUI-8 Chip-to-Module (c2m).
3. W. Wong, What's the Differ-
ence Between NRZ and PAM.
4. Keysight Technologies:
PAM-4 Design Challenges and
the Implications on Test.
5. Isola I-Tera MT40 data sheet.
6. Transmission Line Loss.
7. PCB Material Selection for
High-speed Digital Designs.
8. PCB Dielectric Material
Selection and Fiber Weave Effect
on High-Speed Channel Routing.
9. E. Bogatin, Signal Integ-
rity—Simplified (1st Edition).
10. B. Olney, Effects of Surface
Roughness on High-speed PCBs.
11. J. Coonrod, Choosing Cop-
per Foils for High Frequency PCBs.
12. E. Bogatin, L. Simonovich, S. Gupta, M.
Resso, Practical Analysis of Backplane Vias.
13. E. Bogatin, How long a stub is too long:
Rule of Thumb #18.
14. Size Chart - Footprint Selection.
15. High-Speed Analog Design and Applica-
tion.
16. B. Olney, Return Path Discontinuities.
17. L. Simonovich, Guard Traces.
18. L. Simonovich, Crosstalk.
19. High-Speed Interface Layout Guidelines.
20. 802.3bs-2017 - IEEE Standard for Ether-
net—Amendment 10: Media Access Control
Parameters, Physical Layers, and Management
Parameters for 200 Gb/s and 400 Gb/s Opera-
tion.
21. Keysight Technologies, How to overcome
test challenges in 400G/PAM-4 designs.
Chang Fei Yee is a hardware engineer
with Keysight Technologies. His
responsibilities include embedded
system hardware development, and
signal and power integrity analysis.
Figure 11: Eye diagram at receiver resulted from channel simulation
topology in Figure 10.
