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68 DESIGN007 MAGAZINE I MAY 2018 not only have an impact on the physical real- ization of a design, but also impact the electri- cal signal quality and noise behavior. Graphical topology editing, with constraint- setting including the capability to assign topologies to nets or groups of nets, allows easy constraining with inheritance. Real rout- ing topology extraction and scratchpad editing allow the designer to look at "what if" designs, much like the drawings on the back of the Post-it Note. For instance, what if a memory bus runs at twice its current speed, or a transmission line length is halved? The vital part of the system is that design snapshots (scenarios) can be veri- fied against the constraints and detached from the rest of the real system design as it devel- ops, then be automatically transferred into the constraint database. Those "what-if" sce- narios may behave like a small design on their own; they can be analyzed in the same way for parameters, including signal speeds, cross- talk and distortion. The constraints worked out from such simple sub-design elements can be fed back into the constraint database, thus closing the design loop. It is very important that constraints can be passed/attached at electrical nets (including series passive components like capacitors and resistors), and groups of nets (e.g., buses and net classes) rather than just on a single particu- lar net. This is a great advantage in the con- straining process, as defining constraints for larger systems can then be carried out much faster. Constraints can be reused by importing/ exporting in standard formats such as .XML or .CSV (Figure 4). Closing the Design/Simulation Loop Beside geometrical constraints like net length and spacing, these days electrical requirements such as dedicated delay, delay difference (=skew) or distortion/overshoot have to be met. Signal integrity simulation is much more accurate than using formulas for delay and overshoot evaluation. A key part of the process of constraint-driven design is to have simula- tion available throughout the process to deter- mine whether the constraints are met. This requires a fundamental change in the architec- ture of the tool. Traditionally, SI simulation has been a post- layout process, done after a design has been laid out or the routing determined. With mod- ern constraint-driven tools, the simulation engine is tightly integrated in each operation/ phase of the design flow. SI verification can be performed in both the time-domain and the frequency-domain. Time domain simu- lation has advantages when modeling non- Figure 4: Import/export of constraints.