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80 PCB007 MAGAZINE I FEBRUARY 2019 Lower Cost In addition to the added reliability with microvias, an astute designer can construct a complex interconnect device in a way that lowers overall costs. In The HDI Handbook [3] , which is available for free download, the au- thors go to great lengths to show how layer counts can be reduced using microvia and HDI technology. In the end, it is about wir- ing density. As semiconductor and packag- ing technology drive pin counts up, so goes the wiring density required to support those devices. Thus, one either must increase lay- er counts and reduce line widths and spaces along with higher AR through holes or rede- sign the board with microvias. Increasing lay- er counts, creating finer lines and spaces, and increasing overall cost becomes a significant show stopper. For example, when designing classical PWBs, there is a wiring barrier created by the size of component lands, traces, and vias. If you look at a square inch or PCB real estate, there are only so many SMT land patterns, traces con- nected to the land, and vias connected to the trace that you can put in that one square inch before it is full. Depending on the SMT land size, this barrier is called the wiring density barrier. Understanding the barrier ramifica- tions as well as the cost-density tradeoffs will help the designer (as well as the fabricator) in this endeavor. With through holes, there is a reduction of routing channels, which necessitates an in- crease in layer counts to support wiring den- sities required for today's semiconductor chip technology. If we create more routing channels on the inner layers by placing the blind vias on the surface, we connect more traces per layer, eliminate the through holes on the sur- face, and increase connections. Hence, there is a significant opportunity here to enhance long-term reliability and reduce form factor and overall cost through iterative design using microvia technology. Opportunities to reduce layer counts, dielectric thicknesses, and rout- ing density are among the many benefits of go- ing to HDI type structures. The Importance of Via Formation and Metalization If the blind vias are properly drilled and plated, they will perform with many times the thermal cycle life of typical through holes, but this is not a trivial statement. I discussed many of these issues in my last column. Via shape, cleanliness of the target pad, consistency in the performance of the metalization process, and the electroplated copper uniformity all add up to the reliability of the vias. However, these process steps go hand in hand with the plating processes. One can't expect to enjoy success without the other steps fully optimized. After the desmear process, the next task is to ensure a continuous, conductive, and void-free deposit on the via walls and capture pad. To- day, several processes can be utilized to render vias conductive including: • Conventional electroless copper • Palladium-based direct metallization • Graphite • Carbon black • Conductive polymer These metallization processes (collectively known as "making holes conductive" or MHC) are well developed for both plated through- hole and blind via metallization. Direct metal- lization is applicable to horizontal processing, although vertical systems can also be used. These processes typically involve the deposi- tion of a conductive coating (e.g., palladium, conductive polymer, graphite, carbon black, etc.). This step is then followed by electrolyt- Increasing layer counts, creating finer lines and spaces, and increasing overall cost becomes a significant show stopper.