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54 DESIGN007 MAGAZINE I MAY 2019 tolerance. This would mean that +0.006"/- 0.000" could occur at some point. I can assure you this would not work for a ±0.002" annu- lar ring if the signal pads were only increased by 0.004" to meet an IPC ±0.002" minimum annular ring, and the over-drill for plating was not considered. What about plating tolerances and fabrica- tion route dimensional tolerances, layer-to-lay- er registration tolerances during lamination, or signal integrity tolerances? Again, If we add up all of the accumulative tolerances to build a board, the boards might never get built. So, what is the good news? Some tolerances negate one another, so use true position versus machine tolerance. If both were stated to be ±0.003", we move the fur- thest plus extent on the true position, but we go the other direction on machine tolerance at the minus extent of ±0.003", the two will bal- ance each other out. Add tolerances of ±0.002" layer-to-layer misregistration potential, for in- stance. So, how does the fabricator mitigate the known expansion and contraction based on thin materials? Again, the good news is that most fabricators use a post-etch punch tech- nology. This is where the inner layer cores do not get punched before imaging in a dry-film department. What does this gain us? When the layers are etched and stripped in plating, we have already gone through some of the aque- ous processes that contribute to the expansion and contraction of the core materials, and they get punched after those aqueous processes. In conjunction with that, a scale factor based on the known expansion or contraction of the thickness of the core and material type being used is associated at the CAM department, further mitigating the movement and keeping them within tolerance. 4. Line Edge Acuity In addition, most fabricators utilize a direct image device that helps with line edge acuity. Back in the day, a silver film was produced and plotted with the opposite emulsion. Then, a Di- azo film was produced to be used in manufac- turing, and all of these copies produced a poor- er and poorer line edge quality. Add to that the fact that the old raster plotters had lines of rasterization or a stair-stepped look that also produced poor quality line edges. Today's plot- ters do not do this, and the use of a direct im- age device where the sensitized core is directly imaged with light produces fewer line edge is- sues and better positional accuracy. Typically, these direct image devices even have their own de-ionizing and scavenging systems fully en- closed in the machine, so class 1,000, 10,000, or 100,000 cleanrooms are not needed any- more to reduce the amount of particulate in a given dry-film department. 5. Plating Processes Plating processes have also come a long way from balancing the front to the back of a given panel to achieve the same copper area to allow for more uniform plating. Today, most shops have dual rectification on their plating tanks to allow dialing in the plating distribution. Again, years ago, if you hit a given panel with too much current, you could conceivably plate more in the hole barrels than on the surface, making "hour - glasses" of the holes to check that the current was proper. Now, not only are the plating tanks dual rectified (allowing for better plate distribu- tion) but the panels are also periodically pulled from the tanks and checked with a pin gage to ensure the proper plating on the surface and in the barrel of the holes. 6. Negotiations If the tolerance is too tight, often, negotia- tion is needed. One such negotiation might be warranted for vias. For example, if the via tol- erance is called out as ±.003" for plated vias, and we run into space violations at etch or drill compensation, what can be done? In this case, we ask to change the vias from ±0.003" to +0.003" minus the entire hole size. This al- lows the fabricator to drill the vias smaller, al- lowing for both annular ring and space viola- tions caused by attempting to increase the pad size to keep the vias at ±0.003". In most cas- es, this is acceptable to the end user, as they are true vias and only really require electrical continuity.

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