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PCB007-Aug2019

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56 PCB007 MAGAZINE I AUGUST 2019 Article by Saminda Dharmarathna, Sy Maddux, Chao Benjamin, Ivan Li, William Bowerman, Kesheng Feng, and Jim Watkowski MACDERMID ALPHA ELECTRONICS SOLUTIONS Abstract In this era of electronics miniaturization, high-yield and low-cost integrated circuit (IC) substrates play a crucial role by providing a reliable method of high-density interconnec- tion (HDI) of the chip to the board. To max- imize substrate real estate, the distance be- tween copper traces—also known as line and space (L/S)—should be minimized. Typical PCB technology consists of L/S larger than 40 µ whereas more advanced wafer-level technol- ogy currently sits at or around 2 µm L/S. In the past decade, the chip size has decreased sig- nificantly along with the L/S on the substrate. The decreasing chip scales and smaller L/S distances have created unique challenges for both the printed circuit board (PCB) industry and the semiconductor industry. Fan-out panel-level packaging (FOPLP) is a new manufacturing technology that seeks to bring the PCB world and IC/semiconduc- tor world even closer. While FOPLP is still an emerging technology, the amount of high-vol- ume production in this market space provide a financial incentive to develop innovative solu- tions to enable its ramp-up. The most impor- tant performance aspect of the fine-line plating in this market space is plating uniformity or planarity. Plating uniformity, trace/via top pla- narity (which measures how flat the top of the traces), and vias are a few major features. This is especially important in multilayer process- ing, as nonuniformity on a lower layer can be transferred to successive layers, disrupting the device design with catastrophic consequences, such as short circuits. Additionally, a non-pla- nar surface could also result in signal trans- mission loss by distortion of the connecting points (i.e., vias and traces). Therefore, plat- ing solutions that provide a uniform, planar profile without any special post-treatment are quite desirable. Here, we discuss innovative additive pack- ages for direct-current copper electroplating specifically for IC substrates with capabilities Innovative Electroplating Processes for IC Substrates

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