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92 PCB007 MAGAZINE I AUGUST 2019 turing output update to generate limited depth (blind) drill files for pins in support of VeCS- 2 blind depth structures. 17.2 Padstack Edi- tor supports by-layer keepouts as well as adja- cent layer keepouts to ensure manufacturabil- ity when these structures are used in a layout. These structures are created as library objects, so they can be easily leveraged across many designs for commonly used device escapes. If a structure requires a change, it can be made in one place with all instances refreshed in the layout. VeCS At the moment, we distinguish two "slot" technologies: VeCS-1, where the slots go through the board, and VeCS-2, where we do multi-level blind slots (Figure 1). In practice, we will see more hybrid construc- tions of VeCS-1 and VeCS-2 in one slot. The ad- vantage is that we can connect GND and pow- ers to multiple layers using VeCS-1, and the ad- jacent signal only connects to layer 4, for ex- ample. The VeCS-2 part of the slot creates a stubbles connection, minimizing capacitance and the dispersion of a higher speed signal. At the moment, NextGIn Technology is very much focused on next-generation products, such as very high bandwidth applications where signal transitions between layers can be tuned such that the impedance of the vertical trace matches the impedance of the signal lay- er as it transits from one layer and connects to next. This enables layer transitions with mini- mum loss, enabling more efficient use of rout- ing real estate compared to the ineffective and costly point-to-point routing used today using traditional via technology. VeCS can be combined with through-hole, buried/blind vias, and microvia/HDI technolo- gy. There is no limitation. For example, a VeCS core/multilayer can be sandwiched between a set of microvias on top and bottom. The process flow used right now is as fol- lows: 1. Build board per standard flow. 2. Form slots (optional at mechanical drill stage): VeCS-1 and VeCS-2 from front and back. 3. Complete plating (standard). 4. Fill slots and holes (optional). 5. Form second route and bottom route. 6. Fill slots (second route). 7. Drill through-holes (optional). 8. Complete surface plating similar to a plated over-filled via (POFV). 9. Finish the panel as standard. Setting Up VeCS Design Rules The rules that apply for VeCS are not differ- ent from that used in through-hole/via tech- nology or HDI technology. Overlapping of im- ages (annular ring), slot to copper, second route to slot, etc., are important to have the correct setup. The top view of the VeCS element is shown in Figure 2 as well as all of the different ele- ments of VeCS and a variation with different situations in the vertical trace width by posi- Figure 1: The front slot on the left side shows a VeCS-1, and the right shows VeCS-2. Figure 2: Definition of VeCS parts. Slot width Slot length (variable) 2nd route length Vertical trace width 2nd route Plated slot 2nd Route pitch Bottom route

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