PCB007 Magazine


Issue link: http://iconnect007.uberflip.com/i/1269815

Contents of this Issue


Page 79 of 115

80 PCB007 MAGAZINE I JUNE 2020 HDPUG, after the reliability vehicles are done, will be SI, which will be valuable for the in- dustry. But most of the ones that want to use it for the next generation have already started that simulation, completed it, or are near com- pletion and starting their own SI test vehicles to look at the technology themselves. The industry level interest will be there once multiple OEMs are utilizing it in volume. But by the time they do that, the benefit of achieving that will not be in that generation; it will have to be in the next. Happy, I'm sure you had this with HDI with a blind via, where there's noth- ing routed underneath it. For many designers, that was a three-dimensional paradigm where they could not shift. VeCS is even more because it's not only capable of doing deep blind vias that have nothing routed underneath them, but it has super dense two-dimensional pitch with no issues with CAD, as well as large change routing and areas that are keep-out. This is a real paradigm shift for a conven- tional CAD designer. They're used to copper and laminate; they don't understand a slot or routing down a sidewall. We're at a point now where we're trying to optimize the VeCS trace and physical characteristics with the slot width so that we can create a matched impedance— say at 85 ohms—with the signals running 85 ohms into the VeCS slot, 85 ohms down the slot, and then 85 ohms back to the connec- tions. That is the disruptive technology that I haven't seen even in substrate-level technol- ogy. To be able to do differential continuity all the way down the interconnect and back through to the other chip is unique to VeCS. Holden: Have you created any trenches, or are they all just mechanical? Dickson: Right now, we've been able to do all the way down to 0.35-millimeter interposers with mechanical. The technology is there to do it. The biggest driver for using a laser or not is the cost of the dielectrics. If somebody was willing to pay for non-glass reinforced di- electrics, the HDI concept or laser concept of building the trenches is relatively easy, but we don't need it yet. And the cost is too prohibi- eventually position itself; it will be somewhere in between. And today, what I'm seeing that's going to try to replace that is optical. The next generation of chips is trying to go optical chip- to-chip because there are no other alternatives below 0.8 millimeters on large chips. Holden: If you filled the trenches with an opti- cal polymer waveguide material, VeCS might also be a convenient way to do chip-to-chip optical bussing, along with electrical bussing. Dickson: Correct. The concept is already in the patent. There's embedded optical that you could use with VeCS, but even without optical, say you leave off of it for a second, if you're talking dB per inch—your loss budget—you're looking at the inches of the signal link, which is simplifying it for me. But the SI engineers look at what they have in their budget, and if the lo- cation of their chips is too far apart, they have to come up with an alternate technology to conventional PCB. We're chasing that to match cabling. Our goal is to come up with a signal structure that is nearly as high-performance as a single cable between two chip points. We'll never get there, but that's our goal. And if you use that as your baseline, there are lots of opportunities still left in 28 gigahertz— and maybe even 56 gigahertz—until you get to back panel level structures. Inside of that, inside the 15 inches that you need to route, we can stay in copper all the way through two generations. And that's a significant difference from where the roadmap is today for network and 5G structures. Holden: What we need right now is data on how VeCS improves SI. To the electrical engineers, those graphs show performance they haven't figured out how to meet, and they don't want to go to optical. Dickson: Multiple OEMs already have the simu- lations finished, and the structure concept fin- ished. That part of their step is complete. They already understand the SI benefits. But they're not willing to share any of it because it's indi- vidual IP. The next generation or phase two of

Articles in this issue

Archives of this issue

view archives of PCB007 Magazine - PCB007-July2020