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JULY 2021 I DESIGN007 MAGAZINE 21 Cherie Litson: Put the smallest value cap closest to the power pin. Where the via goes depends upon the type of signal. RF sig- nals prefer to have the via to the plane aer the pin connects to the cap. Digi- tal signals prefer to have the via go directly to the plane and then to the cap. Lee Ritchey: Since virtually all capacitors are surface mount, there is no need for thermal ties between the power vias and the planes. All a designer needs to do is drill a hole in the appropriate plane and make a full contact with the plated through- hole. Carl Schattke: e smallest inductive loop is going to be the least parasitic. In order for the energy to flow in a circuit, the inductive force must be overcome before the voltage will rise. Basically, the spin happens before the push. To reduce the time and energy this takes, we want to minimize the area that has to be energized. is area is going to be the 3D gap between the power trace and the return path. Closer is always better electrically, but if it's too close, though, you start to get into the manufacturing concerns of copper-to-copper plating limita- tions based on copper weights and etch pro- cessing, not to mention the hole-to-hole limi- tations of cracked laminate, and potential CAF problems. Ideally, we place the vias at the edge of the manufacturing tolerances that will not add cost or reduce reliability. Chris Young: In general, when dealing with mul- tiple decoupling capacitors (0.1 mF, 0.01 mF, 0.001 mF values are common) per power pin, a typical approach is to put the smallest-value capacitor closest to the power pin and the larger value as close to the smaller capacitor as possible. is is usually done to shunt noise or interference signals away from the power input of a device. Power vias are usually placed at the largest value capacitor and a trace drawn directly (as possible) from the via to the power pin through the pads of the capacitors. Each decoupling capacitor should have an indepen- dent ground via placed as close as possible to the pads. Keep in mind that traces and space between components should be as small as pos- sible as well while maintaining distances allow for manufacturing capabilities. See Figure 1 for a typical placement of decoupling capacitors near a device. DESIGN007 Figure 1: Typical placement of a decoupling capacitor near a device. (Source: Chris Young)

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