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PCBD-Nov2014

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42 The PCB Design Magazine • November 2014 side. This is due to the width of the trace be- ing much larger than the thickness, so more coupling occurs in the broadside configuration. It is therefore good practice to route adjacent signal layers, in the stackup, orthogonally to each other to minimize the coupling region. A better solution is to only have one signal layer between two planes to totally avoid broadside coupling altogether. Also, these days many stackups use a build- up microstrip layer on the top and bottom of the board. This can be very dangerous as one must take particular care of traces routed on the adjacent layers. Since crosstalk is induced by one or more aggressors onto a victim trace, it is obvious that the higher the aggressor voltage, the more crosstalk will be induced. It is therefore best to segregate groups of nets according to their signal amplitude. This strategy prevents larger voltage nets (3.3V) from affecting smaller volt- age nets (1.5V). Crosstalk is defined by: equation 1 The above equation clearly shows that in or- der to reduce crosstalk, we need to minimize H (height above the plane) and maximize D (dis- tance between traces). The easiest way to reduce crosstalk, from a nearby aggressor signal, is of course by increasing the spacing between the signals in question. Crosstalk falls off very rap- idly with distance. Crosstalk plummets roughly quadratically with increased separation. Dou- bling the spacing cuts the crosstalk to roughly a quarter of its original level. Rule of Thumb: Gap = 3 x trace width. However, in today's complex, dense designs, it is not always possible to use up valuable real estate to satisfy the above. An alternative is to set up parallel segment rules to prevent traces running in parallel for more than 500 mils. Also, the effect of dielectric height above a ref- erence plane on trace-to-trace coupling plays an important role in reducing the crosstalk. A 3 mil thick dielectric material reduces the crosstalk by approximately a quarter, compared to the 6 mil, given the same trace spacing. Rule of Thumb: Couple the signal traces closely to the plane. Crosstalk is typically picked up on long par- allel trace segments. These can be on the same layer as in Figure 3, but may also be broad- side coupled from the adjacent layer. It is for this reason that orthogonal routing is recom- mended on adjacent layers (between planes) to minimize the coupling area. This will not occur with the stackup illustrated in Figure 3 of last month's column, because there is only one sig- nal layer between the planes. So this is very safe as far as broadside crosstalk is concerned. Timing and Skew Flight time delay and skew are key pillars in high-speed PCB design signal integrity. One of the driving factors for flight time and skew performance is the placement of components. Maximum placement refers to the placement in which the distances between the devices are the maximum distance permitted. Controlling the maximum placement of devices, combined with the assumption that good general design practices are adhered to, limits maximum trace beyond design SIGNAL INTEGRITY, PART 2 continues Figure 2: layers 1 and 2 have only 3.4 mils separation and are prone to coupling.

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