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November 2014 • The PCB Design Magazine 43 beyond design SIGNAL INTEGRITY, PART 2 continues delay to roughly the longest Manhattan dis- tance of the signals contained in a specific clock domain. Why the longest Manhattan distance? This is due to skew matching requirements: All of the shorter nets in a clock domain must be length- ened to skew match to the longest run length. Therefore, flight time and skew—for an entire clock domain—are governed by the maximum placement, along with the routing rules that constrain the matching of the trace lengths. In the classic high-speed design flow, tim- ing specifications simulation results are com- pared to determine placement and routing con- straints. Given a length constraint, a designer can control signal integrity by controlling the PCB trace topology of the various parts of an interface. Included in this topology are any ter- minations. Figure 4 illustrates the timing of the clock compared to the address, control and com- mand signals of a DDR3 memory design. Also, the skew between data lanes and data strobes should be kept to a minimum and the eyes should be wide open. DDR3 is much easier to route, in fact, than DDR2 as leveling can be used to synchronize the delay of data lanes. There are many other factors that can influ- ence signal integrity, but basically the stackup planning and the PDN analysis of a PCB are the two main factors that control the stability of a design. Getting these two factors right helps en- sure the long-term reliability and performance of any high-speed digital design. We all know that simulation tools aren't cheap, and there is a learning curve associated with complex software, not to mention that the engineer needs to have years of experience ana- lyzing high-speed designs. By utilizing a board- level simulation service, you can be assured that your PCB will be reliable, manufacturable, will conform to specifications and will pass the rel- Figure 3: Crosstalk on long parallel trace segments.