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44 The PCB Design Magazine • November 2014 evant compliancy tests, saving you time, mon- ey and frustration for a fraction of the cost of board iterations and multiple compliancy test- ing. Plus, the simulation can be done before the design is finalized (before Gerber output or even earlier in the design process) to further reduce production time and costs. Points to Remember • Crosstalk is the unintentional electro- magnetic coupling between traces on a PCB. But crosstalk can also be induced in the return path—which often gets overlooked. • Crosstalk can be coupled trace-to-trace, on the same layer, or can be broadside coupled by traces on adjacent layers. The coupling is three- dimensional. • The higher the aggressor voltage, the more crosstalk will be induced. It is therefore best to segregate groups of nets according to their sig- nal amplitude. • The easiest way to reduce crosstalk, from a nearby aggressor signal, is by increasing the spacing between the signals. • Reducing the dielectric height will also dramatically reduce crosstalk without impact- ing on real estate. • Flight time delay and skew are key pillars in high-speed PCB design signal integrity. One of the driving factors for flight time and skew performance is the placement of components. • Flight time and skew—for an entire clock domain—are governed by the maximum place- ment, along with the routing rules that con- strain the matching of the trace lengths. • Given a length constraint, a designer can control signal integrity by controlling the PCB trace topology of the various parts of an inter- SIGNAL INTEGRITY, PART 2 continues beyond design Figure 4: skew of clock to address, control and command signals of DDr3 memory.