The PCB Design Magazine

PCBD-Jan2016

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54 The PCB Design Magazine • January 2016 by Nicholaus Smith InTegrATeD DeVICe TeCHnology In the portable electronics market, power management integrated circuits (PMICs) are in- creasingly found being packaged into ball grid array (BGA) and chip scale packages (CSP) for their lower material costs, improved electrical performance (no bond wire impedances), and smaller form factors. These advantages do not come without compromise: The silicon die of CSPs are no longer in direct contact with large heat-spreading thermal paddles (E-PADs) used for electrical and thermal conduction. This is the primary performance trade-off; because the IC substrate is not in contact with an E-PAD there is no high-conductivity direct thermal connection from the substrate to the heat-spreading copper planes on the PCB. This article will discuss PCB level methods that will lower the operating temperature of CSP devices by examining methods to transfer heat from the source and transport it to the ambient en- vironment by lowering thermal resistance of the CSP IC. There are usually multiple ways to enhance the performance while simultaneously lowering the operating temperature that can be incorporated into new boards or revisions of ex- isting boards. In order to meet size and weight require- ments, constraints of portable electronic de- signs often force PCB designers to reduce the size of components and PCB real estate area. To meet these demands, the use of CSP packages to shrink the PCB area needed is a common change in designs. As a result of the reduction of total PCB area, the available options to move heat and route high-power PCB traces is also re- duced. Furthermore, the thermal performance cannot be matched when a QFN is compared to an equivalent CSP package; therefore, it is im- perative that the PCB is designed to optimize heat transfer from the CSP to the PCB, which in turn dissipates it into the atmosphere. The pa- rameter measuring the heat conductivity is the junction-to-ambient thermal resistance specifi- cation, Theta-JA (Ө JA (˚C/W)). Just for reference, to match the area utilized for heat transfer when connecting a typical QFN package E-PAD (3x3 mm square) to a CSP device Enhancing Thermal Performance of CSP Integrated Circuits article

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