Issue link: https://iconnect007.uberflip.com/i/626587
30 The PCB Design Magazine • January 2016 In my recent four-part series on stackup planning, I described the best configurations for various stackup requirements. But I did not have the opportunity to delve into the use of planar capacitance to reduce the AC impedance at frequencies above 1GHz, which is the region wherein bypass and decoupling capacitors dra- matically lose their impact. In this column, I will flesh out this topic, and consider the effects of plane resonance on the power distribution network (PDN). Figure 1 illustrates a 12-layer DDR3 board with six routing layers and six plane layers uti- lizing multiple technologies. This board must accommodate 40/80-ohm single-ended/differ- ential impedance for DDR3, 90-ohm differen- tial USB, and the standard 50/100-ohm digital impedances all on the same substrate. In order to reduce the layer count, it is important that these different technologies share the same lay- ers. Plus, one needs to manage the return cur- rent paths and broadside coupling of the strip- line configurations—quite a challenge! The DDR3 matched delay signals are routed on the internal layers 3 & 4 and 9 & 10, which all use ground (GND) as the reference plane. To eliminate broadside coupling, the data lanes (eight in this case), differential strobes, and masks are routed on layers 3 & 4. And the adja- cent traces are routed skewed or orthogonally. The address, control and command signals are routed together with the differential clock on layers 9 & 10. This separates the data lanes and address signals. Since DDR technology utilizes synchronous buses, the signals within the data lanes and within the address bus can be routed closely together, but the eight data lanes should be separated to avoid crosstalk. column by Barry olney In-CIrCuIT DeSIgn PTy lTD AuSTrAlIA BEYoND DESIgN Plane Crazy, Part 2 Figure 1: A 12-layer DDr3 stackup using Isola 370Hr 2gHz material.