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PCBD-Jan2016

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56 The PCB Design Magazine • January 2016 with 0.4 mm pitch one would need to connect nearly 30 CSP pins to maintain an equivalent heat sinking capability based on the area of the E-PAD. Comparative Ө JA datasheet values for the same silicon soldered to similar PCBs under identical electrical loading conditions can vary from 45˚C/W in CSP packages to 25˚C/W for equivalent QFN packages (reference data from the IDTP9023 Wireless Power Receiver) for well- designed PCBs. Such a difference means the CSP will operate at higher temperatures than QFN counterparts. As a consequence, thermal perfor- mance is typically only half as good when an IC is packaged in a CSP package compared to the QFN when both have identical power con- sumption. Thus CSP thermal performance can easily be more than twice as bad as an equiva- lent QFN if not properly compensated for with a well-planned PCB design. The operating temperature of a packaged IC is determined by three factors: convection, conduction, and power burned by the IC to perform the electrical demands. When thermal analysis calculations are solved for CSP ICs us- ing the thermal resistance parameters, it should be noted they are made using an estimate of the number of thermal vias connecting the IC to the PCB. Each connection creates a thermal path that can be used to direct heat away from the IC's semiconducting junctions. These esti- mates assume that the IC is mounted to a 3" x 4.5" solid copper four-layer PCB as defined by JEDEC standard 51. When a real application PCB is being designed, the area is usually much smaller, has cutouts and irregular form factors, many components, multiple vias, and electrical connections that will decrease the thermal per- formance relative to the JEDEC standard. A common dilemma faced by the designer is the challenge of getting the heat developed in the IC to transfer from the device to the at- mosphere through the PCB, with a minimum temperature drop in the thermal pathways. In Figure 1, each pad connected to a com- ponent side trace and each thermal via-in-pad transfers heat from the silicon into the PCB copper planes. Design of the via-in-pad and the number of vias influence the effectiveness of the heat path, as well as the surface area of copper that the vias are in direct contact with. The pitch of the IC under development will in- fluence the size of the hole and proportionally the volume of copper available to conduct the heat (think of the via as a hollow heat-carrying copper cylinder) to the copper surfaces con- nected to the via (i.e., copper planes or traces). Additionally, after the vias-in-pad are built by electroplating, they will need to be filled with a material (non-conductive or conductive) prior to being resurfaced evenly for the installation of the actual CSP device. The via fill material is "poured" into the hole and the packing ratio is usually optimized by the fabricator based on hole diameter. The conductive fill material used to back-fill the vias usually has higher electrical and thermal resis- tance than copper, so the fill material only has a small impact on thermal performance due to article ENHANCINg THERMAL PERFoRMANCE oF CSP INTEgRATED CIRCuITS Figure 1: Cross-section of a PCB-mounted CSP package showing conduction thermal transfer.

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