Design007 Magazine

PCBD-Apr2016

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72 The PCB Design Magazine • April 2016 200 mm with PCB thickness limited to 1.6 mm. The major design challenges that had to be tackled were the 100A current consumption of the FPGA core, the routing of 16 HMC trans- ceivers operating at 15GHz, and the clock tree design for optimal frequency programmability. The design team included one FPGA design- er, one librarian, three PCB designers, two lay- out designers, and a mechanical designer (out- sourced). Xpedition Enterprise was used for board design. The simulation tools used through- out the design phase were Hyperlynx SI, due to their ability to simulate all high speed PCI- Gen3 transceiver channels. For simulations of the optical fiber MicroPOD channels, we used IBIS-AMI channel analysis models. We entered the fast transceivers' constraints into the CES. Package delay was calculated to match all DDR4 to net groups on the PCB. Power integrity sim- ulations were used to verify the PDN structure as designed and to recalculate all required ca- pacitance values. Thermal analysis was done off premises and in parallel to the design. Component Selection All active components used in the design were either engineering samples or new ones at the upmost updated level of technology avail- able off the shelf. Out of several challenges, the two outstanding ones were also in conflict with each other. The first one involved the incoming power from a 12V ATX external PS which had to generate a large variety of sensitive program- mable power supplies on board. In total, we had to distribute 100A to the FPGA core, resulting in a desire for many power layers in the design and stack-up. The second challenge involved the HMC's smallest BGA pitch of 0.65 mm. This small BGA pitch required microvias of 0.41 mm pad, a 0.2 mm hole, and capping requirements that were in contrast to the requirement to use as many power layers as possible. In between, there were also additional parts such as DDR4 2166MHz devices connected to the FPGA core, an HMC memory Gen2 part and optical fibers of 12 lanes to the FPGA. The requirement for very strict and precise power-up and power-down sequences and monitoring features led us to choose Linear Technology modules as a solution. The PCB Stackup Following the design, the next phase is im- plementation. To this end, we contacted about five PCB manufacturers in order to find one that BehinD the scenes: aDcom's tLa aWarD-Winning Design Figure 1: A MicroPOD transceiver.

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