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14 The PCB Design Magazine • July 2016 newer technologies the number of setting op- tions grows exponentially as a larger number of Tx taps are available and trade-offs must be made between Tx and Rx equalization. As such, new tuning techniques are necessary. Further- more, using re-timers to handle excessively long channels (40+ inches) seemed essential in previous generations of serial links. However as PCB and SerDes technologies continue to im- prove—combined with the optimization tech- niques described—we find that re-timers may not necessarily warrant their associated cost, complexity, and real estate. Manufacturing improvements that enhance performance are also described. One example of a short connection with seven discontinuities spread across multiple PCB layers that initial- ly showed multiple impedance changes in the 25% range is demonstrated to become nearly transparent over time. Relentless measurements on bare PCB fabrications, good vendor commu- nication, and manufacturing process improve- ments and controls are key. Breakout traces lon- ger than ¼" should be compensated. However, intentional trace layout manipulation in the presence of impedance control and re-imaging during fabrication must be carefully managed. Dual-diameter via construction is shown to be a viable solution for reducing discontinuities when via lengths exceeds 200 mils, by using simulation confirmed by lab measurement to achieve 20% channel eye improvement in chan- nels of various lengths. SI analysis also verifies acceptable performance in reduced layer-count PCBs to achieve lower cost. This is the fourth in a series of DesignCon papers from the authors, detailing the signal integrity analyses associated with a very large system design. The system is characterized by 7,000+ square inches of circuit board, mul- tiple thousands of interconnected serial links spanning dozens PCBs, operating at 3rd and 4th generation serial link data rates (6 to 12 Gbps). 2. Performance Tuning Using SerDes Setting Optimization This section illustrates system-level SerDes setting optimization performance tuning ex- amples across large, medium, and small sys- tems. For each system, baseline "coded" SerDes settings will be contrasted with "optimized" settings, where "coded" settings represent the previously best-known configuration for the SerDes based on previous simulation and hard- ware testing [4,7,8] . In other words, "coded" repre- sents the settings coded into the system before optimized settings were derived. The system configuration examined re- quired PCBs with newer SerDes technology to interoperate with PCBs using older SerDes technology, as shown in Figure 1. The system integration scenarios involved various connec- tors and modularity, not shown in Figure 1 for simplicity. As newer SerDes (red, at right) can compensate for additional loss, their PCBs typi- NEW SI TECHNIQUES FOR LARGE SYSTEM PERFORMANCE TUNING Figure 1: System configuration combining serdes generations.

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