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PCBD-Sept2017

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42 The PCB Design Magazine • September 2017 that the design can be created correctly for all domains that matter—electrical, mechanical, and manufacturing. Another example is plated through-hole as- pect ratio, which is typically created through improper via selection. The designer has sent the PCB with an overall thickness of .093" and is using a finished hole size of .007" for vias. The PCB fabricator has a best cost-effective plated hole aspect ratio of 10:1. The designer is now informed that the board can be built, but at a higher cost. Now the question is, does the designer spend the time to correct the design, which may take several days or weeks, or eat the extra cost of fabrication? Had the designer been alerted to the via as- pect ratio as the via was placed, this issue would have been recognized the moment the first 7-mil via was placed in the design. When high-volume production comes into play, many design centers use a defined set of rules that is the best common denominator be- tween many fabricators. Based on IPC produc- ibility classes or specific manufacturer rules, it may be possible to design for a more targeted group of manufacturers that can meet new tech- nology requirements. Innovative new tools al- low design teams to create a set of DFM rules targeted for specific technology or manufactur- ing requirements. The rules should be imported into a design at any time to detect how the de- sign sizes up. Conclusion PCB designers are challenged to meet aggres- sive schedules with the highest quality board possible. They take pride in their work. To avoid delaying the project or creating poor-quality boards that may end up costing their employers more to produce the products, designers need a way to avoid DFM errors earlier in the design cycle. Traditional tools that run as a batch are no longer sufficient to avoid discovering issues late in the design cycle. An ounce of prevention is worth a ton of cure at the end. PCBDESIGN Hemant Shah is management group director of Allegro PCB Products at Cadence Design Systems. Ed Acheson is senior principal product engineer for Allegro PCB Products at Cadence Design Systems. Figure 4: Plated through-hole aspect ratio warning avoids creating many instances of this problem in the design. AN OUNCE OF DFM ERROR PREVENTION IS WORTH A POUND OF CURE

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