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20 DESIGN007 MAGAZINE I MARCH 2018 Shaughnessy: What questions are you hearing from hardware designers who are tackling these types of designs? Ferry: The latest version of HyperLynx's new capabili- ties provides solutions to sys- tem-level designers with hard questions along these lines. They're wondering, "Are my implementations possible with various physical constraints and selected board materials? What if I don't have models for my driver or don't know what driver will be, but I just know the standard that it needs to comply to? How can I quickly validate an interface with this specific proto- col standard? How can I model this long inter- connect channel with 3D features in a reason- able amount of time? How can I find problems in my channel design before it's actually full routed?" Our latest HyperLynx solution helps resolve and address these challenges by introducing the new interface compliance analyzer. As part of the solution we have embedded pro- tocol expertise for the common protocols, over 25 are supported, including analysis and verification capabilities needed such as COM- based analysis for Ethernet, as well as built in protocol compliance models that can be used as alternative to IBIS AMI models. Including driver/receiver co-optimization capabilities for the protocol's specified equalization capabili- ties such as CTLE, FFE and DFE. Shaughnessy: Are you doing anything to help the initial aspect of the design process before components have been selected and PCBS routed? Ferry: To aid the up-front what-if analysis design phase, we have introduced the Hyper- Lynx 3D Explorer which allows hardware engineers to easily create, solve and constrain common aspects of the interconnect that need to be solved with a 3D full wave solver. Users can easily select from a wide range of com- mon elements of the intercon- nect such as BGA breakouts, differential vias, series block- ing capacitor configurations or connector pin fields, spec- ify a range of parameters that will create a family of results (generated from a 3D full-wave solver) that are automatically measured against specified frequency domain mask and time domain constraints. This allows users an easy template based method to design the important building blocks of the high-speed channel interconnect will little advance solver knowledge needed. Shaughnessy: How about the post-layout vali- dation phase? Does this version address this aspect of the analysis process? Ferry: For the validation phase, after the PCBs are routed, we've introduced new capability in HyperLynx that allows a fully automated chan - nel decomposition approach. This solution intel- ligently scans channel interconnects of interest, decomposes them into different regions to be solved by optimal solvers. Some regions are optimally solved by 3D electromagnetic solu - tions and others in 2D solutions. This ensures that we have the capacity and performance to accurately solve long channel interconnects. The total solution, including the channel com - pliance analyzer, 3D Exploration capability, as well as the intelligent automated channel extraction really enables us to have the indus - try's best end-to-end high-speed series interface compliance solution in the market. Shaughnessy: Sounds good. Is there anything else we need to cover? Ferry: I think that's everything. Shaughnessy: Thanks for your time, Chuck. Ferry: Thank you, Andy. Always a pleasure. DESIGN007 Chuck Ferry

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