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SMT-Jun2018

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56 SMT007 MAGAZINE I JUNE 2018 that can contribute to voiding in bottom termi- nation components. A single-layer PCB design (Figure 1) was chosen so that other factors (i.e., multilayer board and ground planes) would not influence the key factors being addressed in this study. QFN components of various sizes and pin configurations were among the vari- ables addressed and further defined. In this study, only QFN components were selected (Table 1). There were two types of test boards gener- ated: one with an immersion tin (ImmSn) plat- ing, which is widely used in automotive appli- cation and another with an immersion silver (ImmAg) plating, which is used in high-reli- ability and high-power application. The test board also addressed via design including through hole via, no via, and plugged via configurations under the QFN and LCS components. The through hole via had a 0.3 mm diameter with and 0.5 mm diame- ter resist on top and bottom. The plugged via maintained the same 0.3 mm diameter hole and depth of 0.4 mm with 0.7 mm diameter resist on top and bottom. Vias were configured in a pattern as indicated in Figure 2. The investigation also addressed reflow profile and reflow atmosphere. A low void- ing SAC305, type 4 solder paste was used for this study with solidus temperature of 217°C and liquidus temperature 220°C. Thermocou- ples were strategically placed on the QFN32, and QFN64 component locations on the test vehicle. Proven straight ramp and high soak reflow profiles were evaluated as shown in Figure 3. The straight ramp profile increased at a rate of 1°C/s until reaching liquidus temperature of 220°C. The test vehicle was subjected to 65 seconds above liquidus (TAL) with peak temperature on the test vehicle reaching 240°C. The high-soak reflow profile increased Figure 1: Image of the PCB test vehicle and some of the components used in this DOE. Table 1: Component details. Figure 2: Via design and configuration on the test vehicle.

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