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JUNE 2018 I PCB007 MAGAZINE 45 the surface, while the leveler molecules adsorb selectively on to the high current density areas due to the positively charged, quaternized N group. This prevents over-plating at the edges and avoids premature closure of the via leav- ing voids in the center of the via. Brightener, being a small sulfur-containing molecule, dif- fuses faster into the via and accelerates the plating [8] . Since the geometry of the via chang- es during the plating process, the brightener becomes concentrated inside the via causing a rapid plating in the via. This is called the cur- vature-enhanced-accelerator coverage (CEAC) mechanism [9] . Finally, when the via gets lev- eled with the surface and the plating rates in- side the via and on the surface become equal, the bottom-up filling stops. Conditions and Bath Components Table 1 shows the operational conditions and optimum additive levels. Typically, via fill baths have high copper and low acid to achieve the desired bottom up fill. Test Vehicles Test panels with different via sizes were used during the evaluation. The thickness of the test vehicles used in the process evaluation were 1.6 mm with via diameter range from 75–175 µm, and the via depths of 75 µm and 100 µm. All geometries for each test board thickness were plated at the same time in the same tank and later the fill ratio was calculated by using cross-section analysis. Fill ratio is defined as: Eq. 1 Figure 2 shows a typical cross-section of a filled via with a dimple; dimple is the fill dif- ference A-B. Figure 1: Schematic representation of bottom-up filling. Table 1: Bath components and plating conditions.