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54 DESIGN007 MAGAZINE I JULY 2018 on the eye. However, this only applies to sig- nals within the same group. Asynchronous and unrelated signals, on the other hand, remain sensitive to crosstalk at all times. Unfortunately, due to the ever-increasing speed of digital signals, one may not have the luxury of waiting so long to sample the bus. And as the supply voltage drops from say 3.3V to 1.5V, then the allowable noise margin more than halves making the circuit designer's deci- sions regarding crosstalk even more crucial. Crosstalk creates noise that erodes the noise margin. This noise may not be so great that it alone will cause a bit failure, but it can be enough to push the total noise over the edge. For DDR3 memory devices for instance, the following values are taken from the JEDEC Specification JESD79-3E: The maximum crosstalk value is the dif- ference between the expected voltage at the receiver and the receiver threshold. In this case the maximum crosstalk is 350mV. This is for single-ended signals. Differential technolo- gies do not have the noise margin concerns of single-ended technologies. This is due to com- mon mode rejection, which is the ability of the receiver to reject noise that appears coincident on both inputs. Although differential technolo- gies are much better at rejecting input noise, they are not totally immune. Excessive noise is still an issue and can cause serious problems. Also, the crosstalk depends on the load which may vary considerably when driving banks of memory modules. Keep in mind that the total crosstalk on each victim trace is the total cross- talk from each of several nearby aggressors, all of which sum to produce the maximum value. Figure 3 shows the near-end and far-end crosstalk for the victim traces adjacent to the aggressor trace (1.5V @ 1GHz). In this case Figure 2: Noise margin for DDR3 memory. Figure 3: Near-end and far-end crosstalk for microstrip with 4/4 mil trace width/clearance.

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