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72 DESIGN007 MAGAZINE I JULY 2018 Figure 4: The final stackup structure and dielectric and conductor roughness models. Figure 5: TDR of 10 cm differential links measured and computed (left graphs) and GMS insertion loss (IL) and phase delay for 5 cm differential line segments measured and computed (right graphs) with the identified stackup structure and material models for layer INNER 1 (top graphs) and for layer BOTTOM (bottom graphs).

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