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Design007-July2018

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56 DESIGN007 MAGAZINE I JULY 2018 to maintain the impedance. Keep in mind that the fab costs generally increase below 4 mil trace width. So if real estate is a premium, as it generally is on dense, high-speed designs then reducing the dielectric height may be a good solution. We cannot completely eliminate crosstalk but as PCB designers, it is our job to ascertain how to control, manage and live with the consequences of our decisions. Key Points: • Reducing core voltage also reduces the noise margin. • Crosstalk is caused by the coupling of the electromagnetic fields. • Crosstalk falls off rapidly with the square of the distance and the degree of impact is related to the aggressor signal voltage and proximity. • Synchronous buses benefit from an extraordinary immunity to crosstalk. It only has an impact within a small window around the moment of the clocking. Graphics HyperLynx. Default IC characteristics, crosstalk of 150mV maximum and EMC to FCC Class B are setup in the simulator. The batch mode simulation automatically scans large numbers of nets on the entire PCB, flagging signal integrity, crosstalk and EMC hot spots. Reported crosstalk violations can be evaluated by further interactive simulation if required. Setting the simulator to 150mV maximum crosstalk, on all signals, may seem excessively low, considering the above, but it makes sure we pick up any coupling that may be detrimen- tal to signal integrity when accumulated. I also apply this constraint to synchronous buses to identify the impact of the total crosstalk from all aggressors. It is much easier, and cost effec- tive, to eliminate the source of the noise than to fix the problem further down the product development process. Both forward and reverse crosstalk can be arbitrarily reduced by separating the aggressors from the victim traces or by reducing the height of the dielectric above/below the planes. The latter also requires a reduction in trace width Figure 5: Crosstalk for stripline with 4/4 mil trace width/clearance.

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