Issue link: https://iconnect007.uberflip.com/i/1004549
70 DESIGN007 MAGAZINE I JULY 2018 ers surrounding the strips in the interior lay- ers. The resin-reach layers are required only in cases when test structures have some far end crosstalk (FEXT) and it has to be accounted for in the model. Dielectric constants and loss tan- gents from the PCB manufacturer are shown in brackets in Figure 4 for comparison. In addi- tion to the dielectrics, two conductor rough- ness models are identified—there is nothing to compare it with. The analysis to measurement correlation with all that adjustments and mate- rial models are shown in Figure 5. Comparing to the results with the data from PCB manu- facturer shown in Figure 2, the correlation is much better. Though, it is not perfect due to the expected manufacturing variation and pos- sibly other unknown reasons that we may fur- ther discover. With this new stackup, both pre- and post-layout analysis can be done with high confidence as demonstrated in [1] and [2] . The bottom line is that the stackup data pro- vided by a PCB manufacturer must be vali- dated. Data for strip line layers from this par- ticular manufacturer were basically acceptable for the preliminary analysis of the impedances and delays in the strip lines. Though, data for the traces in the surface layers (microstrips) were not acceptable to do any analysis. Most troubling was the absence of models or any useful data to build conductor roughness mod- parameters and Gamma can be used in Sim- beor to identify the material properties with the separation of the losses between the dielec- tric and conductor roughness [4] . For the accu- rate and unique identification, the geometry of the transmission lines in the test structures must be measured from the cross-sections. The EvR-1 board was cross-sectioned and investi- gated. The final trace widths and separations with an example of the cross-sections are shown in Figure 3. What we can learn from this is that the trace widths and space adjustments from this particular PCB manufacturer were acceptable only for the striplines. However, the geometry of the microstrip traces in the BOTTOM or TOP layers are completely different from the data provided by the manufacturer. That is why we observe more differences in TDR of the microstrips in Figure 2. See more observations and the material identification step details and references in [1] . The final stackup with all geometry adjust- ments from the microphotographs and dielec- tric and conductor roughness models identified with Simbeor software is shown in Figure 4. To ensure the accuracy, we have 8 dielectric models - one for the core dielectric, four for the prepreg layers, one for solder mask dielec- tric and two optional for the resin-reach lay- Figure 3: Final trace geometry adjustments and example of the cross-sections of differential test links in INNER1 and BOTTOM layers (expectations are data from PCB manufacturer).