Issue link: https://iconnect007.uberflip.com/i/1011746
40 PCB007 MAGAZINE I AUGUST 2018 Our fifth presenter Doug Jeffrey of Electrotek discussed their process of drilling blind vias in "Re- liability Findings of Me- chanically Drilled Com- plex Via Structures." Doug went into their process of drilling blind vias and the results of testing these blind vias. They use 0.006" and 0.008" drills for the drilled blind vias and 0.008" and 0.010" for buried vias depending on the aspect ratios. The IPC-2221 D-coupon was used as the test vehicle, as a 14-layer design (1+12+1) with four microvia structures, a buried via set of 2 to 13 and a filled via through via 1 to 14. The two nets consisted of: • Net 1 consists of 800 microvias – Chain 1 is a daisy chain of single layer vias – Chain 2 is a daisy chain of 2 layer stacked microvias • Net 2 consists of 103 buried/through vias and 80 microvias – Chain 1 uses a through via and microvia single-layer daisy chain – Chain 2 consists of a daisy chain of buried vias Testing was done on 1549 coupons from 41 builds conducted from May 2017 to Apr 2018 with four coupons per panel using the new IPC-TM-650 2.6.27 (260°C lead-free profile). Additional reflows were conducted on those that pass for up to 24 such cycles. The test resulted, of the 41 builds, in the failure rates shown in Table 2. A special guest speaker was Stamen Boris- son, of the U.S. Dept. of Commerce, who pre- sented the "Results from DOC Study on U.S. • D-coupon 3 – Net 1 is a single stack microvia with traces used in the daisy chain on layer 2 – Net 2 is a single stack microvia with mini-planes used in the daisy chain on layer 2 • D-coupon 4 – D-Coupon 4 simulates 0402 discretes with via-in-pad and fanned out microvias – Net 1 has via in pad as well as offset microvias and buried via with varying offset microvia to buried via distances – Net 2 has fanned out microvias and the microvias are offset from the buried via with varying offset microvia to buried via distances • D-coupon 5 – D-Coupon 5 simulates 0.5 mm pitched BGA with via-in-pad – Net 1 has via in pad as well as stacked microvias L01-L02 and L02-L03 – Net 2 has via in pad and only a single stack microvia from L01-L02 • D-coupon 6 – D-Coupon 6 simulates SOIC with via-in-pad and fanned out microvias – Net 1 has via in pad as well as offset microvias and buried via with varying offset microvia to buried via distances – Net 2 has fanned out microvias and the microvias are offset from the buried via with varying offset microvia to buried via distances – Peel strip coupon – Peel strip coupon anchored with microvias Testing to be complete by December 2018 and results will be reported at next year's IPC High-Reliability Conference 2019. Table 2: Failure rates of the two nets in the 41 test builds. Doug Jeffrey