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SEPTEMBER 2018 I PCB007 MAGAZINE 59 An example of a full 3D stackup will be pre- sented later. Table 1 represents schematically the possible measures to effectively dissipate the heat (i.e., conducting the excessive pow- er from any die through the various packaging steps to the environment). Thus utilizing (already designed-in) thermal/GND pads on silicon may pro- vide a seamless and most effective heat path from die through the final assembly on a printed circuit board—if the inter- connects on each packaging level are per- formed by copper studs, pillars, bumps— thermal vias and through-holes filled with copper on PCB level respectively. Besides any heat dissipation effects said copper studs, pillars, bumps, cop- per-filled thermal vias and through-ho- les do provide the shortest, extremely re- liable, least parasitics-afflicted electrical interconnects. As being depicted in Figure 3, advanced die designs even utilize forced heatflow prac- tises (e.g., Peltier effect) to additionally cool down hot chips through copper and solder in- terconnects—again, copper filled vias and/ or through-holes become mandatory for utmost thermal effectivity. For clarity of demonstration Figure 3 shows only one of the needed P-layer/N-layer twin pillars needed for driving the Peltier effect. Figure 4 illustrates the breathtaking comple- xity of a smartphone processor package—even several mobile phone generations back. Table 1: Various measures of heat dissipation at various packaging levels. Figure 3: Forced heatflow by Peltier elements. (Source: Nextreme) Figure 4: From die through environment—full packaging complexity. (Source: Prismark/Binghamton University)