Issue link: https://iconnect007.uberflip.com/i/1024460
SEPTEMBER 2018 I PCB007 MAGAZINE 25 Looking at Table 1, we can see the relation- ship between solder pad dimensions and pos- sible trace widths, depending on the number of traces required to pass between the pads. For a "simple" or low I/O count package (Fig- ure 6a) where we only need to route a sin- gle trace in-between the BGA solder pads, it's clear that the maximum trace width is 1/3 of the available space between the pads. In the example shown, we have 300 mm pad pitch, with 150 mm pad diameter, resulting with a recommended line and space requirement of 50 mm. If we now use a more complex package where the higher I/O count requires that two traces need to route through the same pad spacing, the recommended L/S drops to 30 µm, and it's obvious that as pad pitch decreas- es, this will apply further restrictions for line width and separation. As a general summary, the availability of new laser tools will allow for smaller microvias that will be closer together. This will help en- able the use of smaller solder pads on the BGA, and in combination with higher I/O count de- vices, will drive the demand for a reduction in line and space requirements, which will push the HDI roadmap (Figure 7) and continue the move from the existing every-layer production routes into the variations of the semi-additive processes. ELIC, Any-Layer and mSAP The majority of HDI PCBs are currently pro- duced using a subtractive ELIC (every layer in- terconnect) or any-layer technique. The gener- al process flow is outlined in Figure 8. There is a demand for high-end HDI PCBs to move from 40 mm L/S down into the region of 30 mm, and as this can not be achieved with Table 1: L/S required for given pad dimensions. Figure 6: Effect of trace count on dimensions. (Source: Altera) Figure 7: Critical factors within the HDI Roadmap. (Sources: IPC, Jisso, Atotech, customer base)