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32 DESIGN007 MAGAZINE I SEPTEMBER 2018 maximum required frequency (including harmonics). VI. Route the Board Based on Critical Signals Adhere to the defined routing strategy. Clock signals should always have the longest delay of the group. Differential pairs should maintain constant imped- ance along the entire length. VII. Analyze the Return Current Paths All signal traces should be tightly cou- pled to a contiguous reference plane and have a clearly defined minimum loop inductance return current path. VIII. Run the Post-Layout Simulation Simulate critical signals and match sig- nal propagation and timing. Check for signal ringing and eye jitter. IX. Eliminate Crosstalk Scan the board for possible crosstalk. Cross- talk can be coupled trace-to-trace on the same layer or broadside coupled by traces on adja- cent layers. X. Assess Electromagnetic Compliancy (EMC) Control EM radiation at the source. Ensure that differential mode signals do not convert to common mode and eliminate any possible antennae. Without further ado, I will begin with an elaboration of the first rule: Establish design constraints. Complex, high-speed multilayer boards should be designed using a proven design methodology incorporating a pre-layout simu- lation before placing a single chip on the board. This includes reviewing component datasheets and design recommendations prior to the sche- matic capture. Simulation tools can be used to analyze various issues, such as reflections due to impedance discontinuities, crosstalk, signal attenuation, and PDN noise—all of which can impact interconnect performance. Simulation of a PCB design after placement and routing is recommended, but simulation early in the design phase is even better. Both are essential. Pre-layout analyses allow critical interface topologies, termination schemes, and I/O buffer selections to be defined and ana- lyzed for synchronous, source-synchronous, and clock interfaces before placement and rout- ing. Figure 2 depicts a simulated clock signal with (blue) and without (red) a series termina- tion. Simulation opens one's eyes to what the circuitry is doing. It also leads to an enhanced perception of what might be a potential issue once the system is built. There are multiple facets to pre-layout analy- ses, including: • Stackup planning for controlled impedance, signal integrity, and crosstalk • Dielectric material selection for high- frequency operation, manufacturing yield, and cost control • I/O buffer and drive strength selection • Topology optimization for signal integrity, timing, and EMC • Series and parallel termination strategy • Derived layout routing constraints, including trace width, spacing, and delay/ length matching Figure 2: Pre-layout simulation with correction of clock ringing. (Source: HyperLynx)

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