Issue link: https://iconnect007.uberflip.com/i/1028393
SEPTEMBER 2018 I DESIGN007 MAGAZINE 33 • PDN analysis and decoupling capacitor optimization • Signal integrity analysis to meet the design specifications with respect to noise margins, timing, skew, crosstalk, and signal distortion Pre-layout simulations also allow a designer to identify and eliminate signal integrity, cross- talk, and EMC issues early in the design pro- cess. This is the most cost-effective way to design a board with fewer iterations. However, if you do not have access to simulation tools, then follow best practices from Design007 Magazine, IC manufacturers guidelines, etc. While designs continue to increase in com- plexity and time-to-market remains critical, it is imperative to have a constraint system that is integral to your design flow. The constraints— based on a pre-layout simulation—manufactur- ing restrictions, and IC manufacturer's recom- mendations and guidelines should flow from pre-schematic to PCB layout, routing, fabrica- tion, and assembly. Before starting placement and routing, detailed interconnect routing constraints should be established (Figure 3). Of course, these are based on the pre-layout simulation and impedance requirements. Firstly, deter- mine the single-ended and differential imped- ance required for each technology used. Syn- chronous bus delay or length matching should be set up in the constraints editor along with differential pair rules and clearance between signal groups to prevent crosstalk while giving priority to critical signals. Appropriate grouping and defining of net and constraint classes in the early stages of the design process significantly simplifies con- straint definition and management. Grouped constraints can increase layout efficiency, reduce design time, and ultimately lower PCB design costs. The prime objective behind setting con- straints up front is to ensure that the design is going to perform to expectations. It is essen- tial that the system can alert the designer to any errors as they occur. Interactive design rule Figure 3: Typical high-speed design constraints. (Source: PADS Professional Constraint Manager)