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48 DESIGN007 MAGAZINE I OCTOBER 2018 noise margins also decrease, which makes it even more critical to match the impedance. Figure 2 shows differential pairs set up to accommodate three different technologies on the same layers of the substrate. Notice how the signal traces are tightly cou- pled to the reference planes. This helps prevent unwanted radiation, particularly on the outer microstrip signals. The center dielectric material (between layers 5 and 6) is also very thin (2.3 mils) and provides low- impedance planar capaci - tance to the power distri- bution networks (PDNs). Unfortunately, drivers do not have the same imped- ance as the transmission line (typically 10–35 ohms), so terminations are used to balance the impedance, match the line, and mini - mize reflections. Reflec- tions occur whenever the impedance of the transmis- sion line changes along its length. This can be caused by unmatched drivers/ loads, layer transitions, different dielectric mate- rials, stubs, vias, connectors, and integrated-cir- cuit (IC) packages. By understanding the causes of these reflections and eliminating the source of the mismatch, a design can be engineered with reliable performance. Figure 3 shows how using a 12-mA LVC- MOS 1.8-V driver of a Spartan 6 FPGA and an 18.7-ohm series resistor is required to match the driver to the 51.67-ohm trace on the outer Figure 2: 10 Layer stackup with matched Ethernet, DDR3, and USB impedances (iCD Stackup Planner). Figure 3: Matching the Spartan 6 driver to the transmission line (iCD Termination Planner).

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