Issue link: https://iconnect007.uberflip.com/i/1040234
50 DESIGN007 MAGAZINE I OCTOBER 2018 straints. Given a length constraint, a designer can manage signal integrity by controlling the PCB trace topology of the various parts of an interface. Figure 6 (left) shows the required placement for T-topology routing of a DDR2 controller and memory chips. The purpose of the placement guide is to limit the maximum trace lengths and allow for routing and via space, which can be a challenge. This placement does not restrict whether these devices are placed on the top or bottom of the board. The region of the board used for DDR2 circuitry must be iso- lated from other signals. The DDR2 keep-out region is defined for this purpose and shown in Figure 6 (right). The 1.8-V power plane should cover this entire region, and non-DDR2 signals should be kept out of this region. Controlling the placement of devices minimizes interac- tion between different logic families, limits maximum trace length, reduces flight time delay and skew, and assists in complying with timing specifications. Key Points: • The impedance of the driver must match the transmission line for perfect energy transfer • Digital design typically uses a character- istic impedance of 50–60 ohms; however, different technologies have specific impedance requirements • Associated noise margins decrease as operating voltages decrease the field-programmable gate array (FPGA), the return current path will be directly below that trace and will not wander into nearby sections. Route fences also control the auto- router by preventing signals from crossing and allowing the control signals to pass. Addition- ally, a disconcerting problem with high-speed boards is that their failure mode may be inter- mittent behavior across multiple manufactur- ing runs. In this case, the proper layout of the PCB may mean the difference between a reli- able product and a board that performs inter- mittently. Moreover, flight time delay and skew are key concerns in high-speed PCB design. One of the driving factors for flight time and skew performance is the placement of compo- nents. Controlling the maximum placement of devices, combined with the assumption that good design practices are adhered to, limits the maximum signal delay to approximately the longest Manhattan (X + Y) distance of the signals contained in a specific clock domain. Why the longest Manhattan distance? This is due to skew matching requirements. All of the shorter nets in a clock domain must be length- ened to skew match to the longest run length. Therefore, flight time and skew for an entire clock domain are governed by the maximum placement, along with the routing rules that constrain the matching of the trace lengths. In the classic high-speed design flow, timing specifications and simulation results are com- pared to determine placement and routing con- Figure 6: Processor and memory device placement requirements and 1.8-V plane.